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authorClaudiu Zissulescu <claziss@synopsys.com>2017-06-01 11:42:06 +0200
committerClaudiu Zissulescu <claziss@gcc.gnu.org>2017-06-01 11:42:06 +0200
commit23c98523af986d9515db70a3fec3b88a9aab1f53 (patch)
tree750e7762e8f2383f1c561b41a7b8841cbefc2492
parent0f75b66845b1ae16de13f02234d4c9be8193f49e (diff)
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[ARC] Allow r30 to be used by the reg-alloc.
gcc/ 2018-06-01 Claudiu Zissulescu <claziss@synopsys.com> * config/arc/arc.c (arc_conditional_register_usage): Allow r30 to be used by the reg-alloc. From-SVN: r248778
-rw-r--r--gcc/ChangeLog5
-rw-r--r--gcc/config/arc/arc.c9
-rw-r--r--gcc/config/arc/arc.h3
3 files changed, 15 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 909c1dd..743f468 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,10 @@
2017-06-01 Claudiu Zissulescu <claziss@synopsys.com>
+ * config/arc/arc.c (arc_conditional_register_usage): Allow r30 to
+ be used by the reg-alloc.
+
+2017-06-01 Claudiu Zissulescu <claziss@synopsys.com>
+
* config/arc/arc.md (mulsi3): Avoid use of hard registers before
reg-alloc when having mul64 or mul32x16 instructions.
(mulsidi3): Likewise.
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 42730d5..a45e12b 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1548,7 +1548,14 @@ arc_conditional_register_usage (void)
/* For ARCv2 the core register set is changed. */
strcpy (rname29, "ilink");
strcpy (rname30, "r30");
- fixed_regs[30] = call_used_regs[30] = 1;
+ call_used_regs[30] = 1;
+ fixed_regs[30] = 0;
+
+ arc_regno_reg_class[30] = WRITABLE_CORE_REGS;
+ SET_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], 30);
+ SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], 30);
+ SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], 30);
+ SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], 30);
}
if (TARGET_MUL64_SET)
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 52f121f..5627eb4 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -641,7 +641,8 @@ extern enum reg_class arc_regno_reg_class[];
((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) \
|| ((unsigned) reg_renumber[REGNO] < 29) \
|| ((unsigned) (REGNO) == (unsigned) arc_tp_regno) \
- || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)))
+ || (fixed_regs[REGNO] == 0 && IN_RANGE (REGNO, 32, 59)) \
+ || ((REGNO) == 30 && fixed_regs[REGNO] == 0))
#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)