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| author | Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> | 2023-01-19 12:43:55 +0530 |
|---|---|---|
| committer | Prathamesh Kulkarni <prathamesh.kulkarni@linaro.org> | 2023-01-19 12:46:08 +0530 |
| commit | 22c75b4ed94bd731cb6e37c507de1d91954a17cf (patch) | |
| tree | faad56f2ff8c529707f7976abaafaf2723ed1153 | |
| parent | 3c99493bf39a7fef9213e6f5af94b78bb15fcfdc (diff) | |
| download | gcc-22c75b4ed94bd731cb6e37c507de1d91954a17cf.zip gcc-22c75b4ed94bd731cb6e37c507de1d91954a17cf.tar.gz gcc-22c75b4ed94bd731cb6e37c507de1d91954a17cf.tar.bz2 | |
[aarch64] Use exact_log2 (INTVAL (operands[2])) >= 0 to gate for vec_merge patterns.
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md (aarch64_simd_vec_set<mode>): Use
exact_log2 (INTVAL (operands[2])) >= 0 as condition for gating
the pattern.
(aarch64_simd_vec_copy_lane<mode>): Likewise.
(aarch64_simd_vec_copy_lane_<vswap_width_name><mode>): Likewise.
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 31d9e89..7f212bf 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -1064,7 +1064,7 @@ (match_operand:<VEL> 1 "aarch64_simd_nonimmediate_operand" "w,?r,Utv")) (match_operand:VALL_F16 3 "register_operand" "0,0,0") (match_operand:SI 2 "immediate_operand" "i,i,i")))] - "TARGET_SIMD" + "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" { int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT ((HOST_WIDE_INT) 1 << elt); @@ -1093,7 +1093,7 @@ [(match_operand:SI 4 "immediate_operand" "i")]))) (match_operand:VALL_F16 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] - "TARGET_SIMD" + "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" { int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt); @@ -1114,7 +1114,7 @@ [(match_operand:SI 4 "immediate_operand" "i")]))) (match_operand:VALL_F16_NO_V2Q 1 "register_operand" "0") (match_operand:SI 2 "immediate_operand" "i")))] - "TARGET_SIMD" + "TARGET_SIMD && exact_log2 (INTVAL (operands[2])) >= 0" { int elt = ENDIAN_LANE_N (<nunits>, exact_log2 (INTVAL (operands[2]))); operands[2] = GEN_INT (HOST_WIDE_INT_1 << elt); |