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| author | Jakub Jelinek <jakub@redhat.com> | 2018-03-14 09:48:40 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2018-03-14 09:48:40 +0100 |
| commit | 2062c40cb5deeea3ef964c7f5bb8a48b3d38831e (patch) | |
| tree | 63f18fc6904cbb2022bfdda4dc900f6932182093 | |
| parent | ec64ffc8501c20efdebefb494f3c90ab44199b60 (diff) | |
| download | gcc-2062c40cb5deeea3ef964c7f5bb8a48b3d38831e.zip gcc-2062c40cb5deeea3ef964c7f5bb8a48b3d38831e.tar.gz gcc-2062c40cb5deeea3ef964c7f5bb8a48b3d38831e.tar.bz2 | |
re PR target/84844 (ICE in extract_constrain_insn_cached, at recog.c:2217 (error: insn does not satisfy its constraints))
PR target/84844
Revert
2017-04-20 Uros Bizjak <ubizjak@gmail.com>
PR target/78090
* config/i386/constraints.md (Yc): New register constraint.
* config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed):
Use Yc constraint for alternative 2 of operand 0. Remove
preferred_for_speed attribute.
* gcc.target/i386/pr84844.c: New test.
From-SVN: r258515
| -rw-r--r-- | gcc/ChangeLog | 12 | ||||
| -rw-r--r-- | gcc/config/i386/constraints.md | 5 | ||||
| -rw-r--r-- | gcc/config/i386/i386.md | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr84844.c | 10 |
5 files changed, 32 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 550e2b6..3e174c5 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,15 @@ +2018-03-14 Jakub Jelinek <jakub@redhat.com> + + PR target/84844 + Revert + 2017-04-20 Uros Bizjak <ubizjak@gmail.com> + + PR target/78090 + * config/i386/constraints.md (Yc): New register constraint. + * config/i386/i386.md (*float<SWI48:mode><MODEF:mode>2_mixed): + Use Yc constraint for alternative 2 of operand 0. Remove + preferred_for_speed attribute. + 2018-03-14 Richard Biener <rguenther@suse.de> PR tree-optimization/84830 diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index d026968..f9564d3 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -99,7 +99,6 @@ ;; We use the Y prefix to denote any number of conditional register sets: ;; z First SSE register. -;; c SSE inter-unit conversions enabled ;; i SSE2 inter-unit moves to SSE register enabled ;; j SSE2 inter-unit moves from SSE register enabled ;; d any EVEX encodable SSE register for AVX512BW target or any SSE register @@ -124,10 +123,6 @@ (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS" "First SSE register (@code{%xmm0}).") -(define_register_constraint "Yc" - "TARGET_SSE && TARGET_INTER_UNIT_CONVERSIONS ? ALL_SSE_REGS : NO_REGS" - "@internal Any SSE register, when SSE and inter-unit conversions are enabled.") - (define_register_constraint "Yi" "TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC ? ALL_SSE_REGS : NO_REGS" "@internal Any SSE register, when SSE2 and inter-unit moves to vector registers are enabled.") diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index bd44243..2b73e8f 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5325,7 +5325,7 @@ }) (define_insn "*float<SWI48:mode><MODEF:mode>2_mixed" - [(set (match_operand:MODEF 0 "register_operand" "=f,Yc,v") + [(set (match_operand:MODEF 0 "register_operand" "=f,v,v") (float:MODEF (match_operand:SWI48 1 "nonimmediate_operand" "m,r,m")))] "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH" @@ -5354,6 +5354,10 @@ && X87_ENABLE_FLOAT (<MODEF:MODE>mode, <SWI48:MODE>mode)") ] + (symbol_ref "true"))) + (set (attr "preferred_for_speed") + (cond [(eq_attr "alternative" "1") + (symbol_ref "TARGET_INTER_UNIT_CONVERSIONS")] (symbol_ref "true")))]) (define_insn "*float<SWI48x:mode><MODEF:mode>2_i387" diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 0175d43..215e302 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2018-03-14 Jakub Jelinek <jakub@redhat.com> + + PR target/84844 + * gcc.target/i386/pr84844.c: New test. + 2018-03-14 Richard Biener <rguenther@suse.de> PR tree-optimization/84830 diff --git a/gcc/testsuite/gcc.target/i386/pr84844.c b/gcc/testsuite/gcc.target/i386/pr84844.c new file mode 100644 index 0000000..16e1416 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr84844.c @@ -0,0 +1,10 @@ +/* PR target/84844 */ +/* { dg-do compile } */ +/* { dg-options "-march=bdver1 -O2 -fschedule-insns -fselective-scheduling" } */ + +double +foo (int *x, int y, int z) +{ + *x = y; + return z; +} |