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| author | Haochen Jiang <haochen.jiang@intel.com> | 2023-07-21 15:43:30 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2023-07-21 15:52:19 +0800 |
| commit | 1ec65c2bc076b2909ee2ac0667757201d8b3c757 (patch) | |
| tree | 741f5732187713d2e35987e402f26e79183cb4a8 | |
| parent | 9f8f37f5490076b10436993fb90d18092a960922 (diff) | |
| download | gcc-1ec65c2bc076b2909ee2ac0667757201d8b3c757.zip gcc-1ec65c2bc076b2909ee2ac0667757201d8b3c757.tar.gz gcc-1ec65c2bc076b2909ee2ac0667757201d8b3c757.tar.bz2 | |
Fix a typo
Hi all,
This patch fix a typo which will not cause any behavior difference.
Commited as obvious change.
Thx,
Haochen
gcc/ChangeLog:
* config/i386/i386.opt: Fix a typo.
| -rw-r--r-- | gcc/config/i386/i386.opt | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index db99568..1cc8563 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -1289,11 +1289,6 @@ Target Mask(ISA2_SM3) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and SM3 built-in functions and code generation. -mvpinsrvpextr -Target Mask(ISA2_VPINSRVPEXTR) Var(ix86_isa_flags2) Save -Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, -AVX512VL and VPINSRVPEXTR built-in functions and code generation. - msha512 Target Mask(ISA2_SHA512) Var(ix86_isa_flags2) Save Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX and |