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| author | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-18 20:24:26 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-18 20:32:36 +0800 |
| commit | 1b03c73295266984378dd9da99a9458b591b964c (patch) | |
| tree | 19f2bde0ac6f04fcb3b82a70110b251260fb3ed5 | |
| parent | fc7070025d1a6668ff6cb4391f84771a7662def7 (diff) | |
| download | gcc-1b03c73295266984378dd9da99a9458b591b964c.zip gcc-1b03c73295266984378dd9da99a9458b591b964c.tar.gz gcc-1b03c73295266984378dd9da99a9458b591b964c.tar.bz2 | |
RISC-V: Removed misleading comments in testcases
This patch removed the misleading comments in testcases since we
support fold min(int, poly) to constant by this patch
(https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629651.html).
Thereby the csrr will not appear inside the assembly code, even if there
is no support for some VLS vector patterns.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/div-1.c: Removed comments.
* gcc.target/riscv/rvv/autovec/vls/shift-3.c: Ditto.
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c | 1 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c index 40224c6..e36fa9d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/div-1.c @@ -54,5 +54,4 @@ DEF_OP_VV (div, 256, int64_t, /) DEF_OP_VV (div, 512, int64_t, /) /* { dg-final { scan-assembler-times {vdivu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ -/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division. */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c index b34a349..db2295b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-3.c @@ -54,5 +54,4 @@ DEF_OP_VV (shift, 256, int64_t, <<) DEF_OP_VV (shift, 512, int64_t, <<) /* { dg-final { scan-assembler-times {vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 41 } } */ -/* TODO: Ideally, we should make sure there is no "csrr vlenb". However, we still have 'csrr vlenb' for some cases since we don't support VLS mode conversion which are needed by division. */ /* { dg-final { scan-assembler-not {csrr} } } */ |