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| author | Yanzhang Wang <yanzhang.wang@intel.com> | 2023-04-26 21:06:02 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-05-02 23:31:43 +0800 |
| commit | 1adb1a653d6739589b12337c974c7e741cfb187c (patch) | |
| tree | 1d44a3c0562631a14dadcefa3160fd9c3446044a | |
| parent | 87c347c2897537a6aa391efbfc5ed00c625434fe (diff) | |
| download | gcc-1adb1a653d6739589b12337c974c7e741cfb187c.zip gcc-1adb1a653d6739589b12337c974c7e741cfb187c.tar.gz gcc-1adb1a653d6739589b12337c974c7e741cfb187c.tar.bz2 | |
RISC-V: ICE for vlmul_ext_v intrinsic API
PR target/109617
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Support VNx2HI and VNX4DI when MIN_VLEN >= 128.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlmul_ext-1.c: New test.
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Co-authored-by: Pan Li <pan2.li@intel.com>
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
| -rw-r--r-- | gcc/config/riscv/vector-iterators.md | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c | 14 |
2 files changed, 16 insertions, 1 deletions
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index a8e8561..0336599 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -189,6 +189,7 @@ (VNx1HI "TARGET_MIN_VLEN < 128") VNx2HI VNx4HI VNx8HI (VNx16HI "TARGET_MIN_VLEN >= 128") (VNx1SI "TARGET_MIN_VLEN < 128") VNx2SI VNx4SI (VNx8SI "TARGET_MIN_VLEN >= 128") (VNx1DI "TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN < 128") (VNx2DI "TARGET_VECTOR_ELEN_64") + (VNx4DI "TARGET_VECTOR_ELEN_64") (VNx1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN < 128") (VNx2SF "TARGET_VECTOR_ELEN_FP_32") (VNx4SF "TARGET_VECTOR_ELEN_FP_32") @@ -220,7 +221,7 @@ (define_mode_iterator VLMULEXT32 [ (VNx1QI "TARGET_MIN_VLEN < 128") VNx2QI (VNx4QI "TARGET_MIN_VLEN >= 128") - (VNx1HI "TARGET_MIN_VLEN < 128") + (VNx1HI "TARGET_MIN_VLEN < 128") (VNx2HI "TARGET_MIN_VLEN >= 128") ]) (define_mode_iterator VLMULEXT64 [ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c new file mode 100644 index 0000000..501d98c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include <riscv_vector.h> + +vint16m8_t test_vlmul_ext_v_i16mf4_i16m8(vint16mf4_t op1) { + return __riscv_vlmul_ext_v_i16mf4_i16m8(op1); +} + +vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) { + return __riscv_vlmul_ext_v_i64m2_i64m8(op1); +} + +/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */ |