*** empty log message ***

From-SVN: r623

5 files changed, 231 insertions, 12 deletions

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index ed6d27d..14a9428 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3633,6 +3633,42 @@
   "TARGET_80387"
   "* return (char *) output_387_binary_op (insn, operands);")
 
+(define_expand "strlensi"
+  [(parallel [(set (match_dup 4)
+		   (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" ""))
+			       (match_operand:QI 2 "register_operand" "")
+			       (match_operand:SI 3 "immediate_operand" "")] 0))
+	      (clobber (match_dup 1))])
+   (set (match_dup 5)
+	(not:SI (match_dup 4)))
+   (set (match_operand:SI 0 "register_operand" "")
+	(minus:SI (match_dup 5)
+		 (const_int 1)))]
+  ""
+  "
+{
+  operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
+  operands[4] = gen_reg_rtx (SImode);
+  operands[5] = gen_reg_rtx (SImode);
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=&c")
+	(unspec:SI [(mem:BLK (match_operand:SI 1 "register_operand" "D"))
+		    (match_operand:QI 2 "register_operand" "a")
+		    (match_operand:SI 3 "immediate_operand" "i")] 0))
+   (clobber (match_dup 1))]
+  ""
+  "*
+{
+  rtx xops[2];
+
+  xops[0] = operands[0];
+  xops[1] = constm1_rtx;
+  output_asm_insn (AS2 (mov%L0,%1,%0), xops);
+  return \"repnz\;scas%B2\";
+}")
+
 ;;- Local variables:
 ;;- mode:emacs-lisp
 ;;- comment-start: ";;- "
diff --git a/gcc/config/i386/x-ncr3000 b/gcc/config/i386/x-ncr3000
index 1af09c5..6dc009f 100644
--- a/gcc/config/i386/x-ncr3000
+++ b/gcc/config/i386/x-ncr3000
@@ -1,3 +1,21 @@
+# Makefile additions for the NCR3000 as host system.
+
+# Using -O with the AT&T compiler fails, with a message about a missing
+# /usr/ccs/lib/optim pass.  So override the default in Makefile.in
+
+CCLIBFLAGS=
+
+# NCR3000 ships with a MetaWare compiler installed as CC, which chokes and
+# dies all over the place on GCC source.  However, the AT&T compiler,
+# crusty as it is, can be used to bootstrap GCC.  It can be found in
+# /usr/ccs/ATT/cc.  It is also used to compile the things that should
+# not be compiled with GCC.
+
+CC = /usr/ccs/ATT/cc
+OLDCC = /usr/ccs/ATT/cc
+
+# The rest is just x-i386v4.
+
 # The svr4 reference port for the i386 contains an alloca.o routine
 # in /usr/ucblib/libucb.a, but we can't just try to get that by
 # setting CLIB to /usr/ucblib/libucb.a because (unfortunately)
diff --git a/gcc/config/sparc/sysv4.h b/gcc/config/sparc/sysv4.h
index f87784d..b7b7ffe 100644
--- a/gcc/config/sparc/sysv4.h
+++ b/gcc/config/sparc/sysv4.h
@@ -1,5 +1,5 @@
 /* Target definitions for GNU compiler for Sparc running System V.4
-   Copyright (C) 1991 Free Software Foundation, Inc.
+   Copyright (C) 1991, 1992 Free Software Foundation, Inc.
 
    Written by Ron Guilmette (rfg@ncd.com).
 
@@ -20,30 +20,164 @@ along with GNU CC; see the file COPYING.  If not, write to
 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
 
 #include "sparc.h"
+
+/* Undefine some symbols which are defined in "sparc.h" but which are
+   appropriate only for SunOS 4.x, and not for svr4.  */
+
+#undef DBX_DEBUGGING_INFO
+#undef WORD_SWITCH_TAKES_ARG
+#undef SELECT_SECTION
+#undef ASM_DECLARE_FUNCTION_NAME
+#undef TEXT_SECTION_ASM_OP
+#undef DATA_SECTION_ASM_OP
+
 #include "svr4.h"
 
+/* Undefined some symbols which are defined in "svr4.h" but which are
+   appropriate only for typical svr4 systems, but not for the specific
+   case of svr4 running on a Sparc.  */
+
+#undef CTORS_SECTION_ASM_OP
+#undef DTORS_SECTION_ASM_OP
+#undef INIT_SECTION_ASM_OP
+#undef CONST_SECTION_ASM_OP
+#undef TYPE_OPERAND_FMT
+#undef PUSHSECTION_FORMAT
+#undef STRING_ASM_OP
+#undef COMMON_ASM_OP
+#undef SKIP_ASM_OP
+#undef DEF_ASM_OP	/* Has no equivalent.  See ASM_OUTPUT_DEF below.  */
+#undef ASM_GENERATE_INTERNAL_LABEL
+#undef ASM_OUTPUT_INTERNAL_LABEL
+
 /* Provide a set of pre-definitions and pre-assertions appropriate for
-   the sparc running svr4.  __svr4__ is our extension.  */
+   the Sparc running svr4.  __svr4__ is our extension.  */
 
 #define CPP_PREDEFINES \
   "-Dsparc -Dunix -D__svr4__ -Asystem(unix) -Acpu(sparc) -Amachine(sparc)"
 
+/* This is the string used to begin an assembly language comment for the
+   Sparc/svr4 assembler.  */
+
 #define ASM_COMMENT_START "!"
 
-#undef TYPE_OPERAND_FMT
+/* Define the names of various pseudo-op used by the Sparc/svr4 assembler.
+   Note that many of these are different from the typical pseudo-ops used
+   by most svr4 assemblers.  That is probably due to a (misguided?) attempt
+   to keep the Sparc/svr4 assembler somewhat compatible with the Sparc/SunOS
+   assembler.  */
+
+#define STRING_ASM_OP		"\t.asciz"
+#define COMMON_ASM_OP		"\t.common"
+#define SKIP_ASM_OP		"\t.skip"
+#define UNALIGNED_INT_ASM_OP	"\t.uaword"
+#define UNALIGNED_SHORT_ASM_OP	"\t.uahalf"
+#define PUSHSECTION_ASM_OP	"\t.pushsection"
+#define POPSECTION_ASM_OP	"\t.popsection"
+
+/* This is the format used to print the second operand of a .type pseudo-op
+   for the Sparc/svr4 assembler.  */
+
 #define TYPE_OPERAND_FMT      "#%s"
 
-/* Define how the sparc registers should be numbered for Dwarf output.
+/* This is the format used to print a .pushsection pseudo-op (and its operand)
+   for the Sparc/svr4 assembler.  */
+
+#define PUSHSECTION_FORMAT	"%s\t\"%s\"\n"
+
+/* This is how to equate one symbol to another symbol.  The syntax used is
+   `SYM1=SYM2'.  Note that this is different from the way equates are done
+   with most svr4 assemblers, where the syntax is `.set SYM1,SYM2'.  */
+
+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
+ do {	fprintf ((FILE), "\t");						\
+	assemble_name (FILE, LABEL1);					\
+	fprintf (FILE, " = ");						\
+	assemble_name (FILE, LABEL2);					\
+	fprintf (FILE, "\n");						\
+  } while (0)
+
+/* Generate the special assembly code needed to align the start of a jump
+   tables.  Under svr4, jump tables go into the .rodata section.  Other
+   things (e.g. constants) may be put into the .rodata section too, and
+   those other things may end on odd (i.e. unaligned) boundaries, so we
+   need to get re-aligned just before we output each jump table.  */
+
+#define ASM_OUTPUT_ALIGN_JUMP_TABLE(FILE) ASM_OUTPUT_ALIGN ((FILE), 2)
+
+/* This is how to output an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.
+
+   If the NUM argument is negative, we don't use it when generating the
+   label.
+
+   For most svr4 systems, the convention is that any symbol which begins
+   with a period is not put into the linker symbol table by the assembler,
+   however the current Sparc/svr4 assembler is brain-dammaged and it needs
+   to see `.L' at the start of a symbol or else it will be put into the
+   linker symbol table.
+*/
+
+#define ASM_OUTPUT_INTERNAL_LABEL(FILE, PREFIX, NUM)			\
+do {									\
+  if ((int) (NUM) >= 0)							\
+    fprintf (FILE, ".L%s%d:\n", PREFIX, NUM);				\
+  else									\
+    fprintf (FILE, ".L%s:\n", PREFIX);					\
+} while (0)
+
+/* This is how to store into the string LABEL
+   the symbol_ref name of an internal numbered label where
+   PREFIX is the class of label and NUM is the number within the class.
+   This is suitable for output with `assemble_name'.
+
+   If the NUM argument is negative, we don't use it when generating the
+   label.
+
+   For most svr4 systems, the convention is that any symbol which begins
+   with a period is not put into the linker symbol table by the assembler,
+   however the current Sparc/svr4 assembler is brain-dammaged and it needs
+   to see `.L' at the start of a symbol or else it will be put into the
+   linker symbol table.
+*/
+
+#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM)			\
+do {									\
+  if ((int) (NUM) >= 0)							\
+    sprintf (LABEL, "*.L%s%d", PREFIX, NUM);				\
+  else									\
+    sprintf (LABEL, "*.L%s", PREFIX);					\
+} while (0)
+
+/* Define how the Sparc registers should be numbered for Dwarf output.
    The numbering provided here should be compatible with the native
-   svr4 SDB debugger in the sparc/svr4 reference port.  */
+   svr4 SDB debugger in the Sparc/svr4 reference port.  The numbering
+   is as follows:
+
+   Assembly name	gcc internal regno	Dwarf regno
+   ----------------------------------------------------------
+   g0-g7		0-7			0-7
+   o0-o7		8-15			8-15
+   l0-l7		16-23			16-23
+   i0-i7		24-31			24-31
+   f0-f31		32-63			40-71
+*/
 
 #define DBX_REGISTER_NUMBER(REGNO)					\
-  ((REGNO) < 32) ? (REGNO) : ((REGNO) + 8))
+  (((REGNO) < 32) ? (REGNO)						\
+   : ((REGNO) < 63) ? ((REGNO) + 8)					\
+   : (abort (), 0))
 
-/* A pair of defines for the set of pseudo-ops used to switch to the
-   .ctors and .dtors sections.  Note that on the sparc, all user-defined
-   sections have the "progbits" attribute by default, so we don't even
-   specify it here.  */
+/* A set of symbol definitions for assembly pseudo-ops which will
+   get us switched to various sections of interest.  These are used
+   in all places where we simply want to switch to a section, and
+   *not* to push the previous section name onto the assembler's
+   section names stack (as we do often in dwarfout.c).  */
 
-#define CTORS_SECTION_ASM_OP    "\t.section\t.ctors,\"a\""
-#define DTORS_SECTION_ASM_OP    "\t.section\t.dtors,\"a\""
+#define TEXT_SECTION_ASM_OP	"\t.section\t\".text\""
+#define DATA_SECTION_ASM_OP	"\t.section\t\".data\""
+#define BSS_SECTION_ASM_OP	"\t.section\t\".bss\""
+#define CONST_SECTION_ASM_OP	"\t.section\t\".rodata\""
+#define INIT_SECTION_ASM_OP	"\t.section\t\".init\",#alloc"
+#define CTORS_SECTION_ASM_OP    "\t.section\t\".ctors\",#alloc"
+#define DTORS_SECTION_ASM_OP    "\t.section\t\".dtors\",#alloc"
diff --git a/gcc/expr.h b/gcc/expr.h
index 620a425..a78c262 100644
--- a/gcc/expr.h
+++ b/gcc/expr.h
@@ -320,6 +320,7 @@ extern optab abs_optab;		/* Abs value */
 extern optab one_cmpl_optab;	/* Bitwise not */
 extern optab ffs_optab;		/* Find first bit set */
 extern optab sqrt_optab;	/* Square root */
+extern optab strlen_optab;	/* String length root */
 
 /* Passed to expand_binop and expand_unop to say which options to try to use
    if the requested operation can't be open-coded on the requisite mode.
diff --git a/gcc/optabs.c b/gcc/optabs.c
index d3bd54a..b157853 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -77,6 +77,8 @@ optab cmp_optab;
 optab ucmp_optab;  /* Used only for libcalls for unsigned comparisons.  */
 optab tst_optab;
 
+optab strlen_optab;
+
 /* SYMBOL_REF rtx's for the library functions that are called
    implicitly and not via optabs.  */
 
@@ -2831,6 +2833,7 @@ init_optabs ()
   one_cmpl_optab = init_optab (NOT);
   ffs_optab = init_optab (FFS);
   sqrt_optab = init_optab (SQRT);
+  strlen_optab = init_optab (UNKNOWN);
 
 #ifdef HAVE_addqi3
   if (HAVE_addqi3)
@@ -3716,6 +3719,33 @@ init_optabs ()
   /* No library calls here!  If there is no sqrt instruction expand_builtin
      should force the library call.  */
 
+#ifdef HAVE_strlenqi
+  if (HAVE_strlenqi)
+    strlen_optab->handlers[(int) QImode].insn_code = CODE_FOR_strlenqi;
+#endif
+#ifdef HAVE_strlenhi
+  if (HAVE_strlenhi)
+    strlen_optab->handlers[(int) HImode].insn_code = CODE_FOR_strlenhi;
+#endif
+#ifdef HAVE_strlenpsi
+  if (HAVE_strlenpsi)
+    strlen_optab->handlers[(int) PSImode].insn_code = CODE_FOR_strlenpsi;
+#endif
+#ifdef HAVE_strlensi
+  if (HAVE_strlensi)
+    strlen_optab->handlers[(int) SImode].insn_code = CODE_FOR_strlensi;
+#endif
+#ifdef HAVE_strlendi
+  if (HAVE_strlendi)
+    strlen_optab->handlers[(int) DImode].insn_code = CODE_FOR_strlendi;
+#endif
+#ifdef HAVE_strlenti
+  if (HAVE_strlenti)
+    strlen_optab->handlers[(int) TImode].insn_code = CODE_FOR_strlenti;
+#endif
+  /* No library calls here!  If there is no strlen instruction expand_builtin
+     should force the library call.  */
+
 #ifdef HAVE_one_cmplqi2
   if (HAVE_one_cmplqi2)
     one_cmpl_optab->handlers[(int) QImode].insn_code = CODE_FOR_one_cmplqi2;