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author | Junxian Zhu <zhujunxian@oss.cipunited.com> | 2023-02-17 16:35:56 +0800 |
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committer | YunQiang Su <yunqiang.su@cipunited.com> | 2023-02-24 11:25:32 +0800 |
commit | 19aa3900bca808b49417a7aef295b5f1a583c298 (patch) | |
tree | c2016bbc6be9bc4c614b0fc4d9e40f731b0fd352 | |
parent | a3a45f0b145ae9381ce3daa75db17c43a76ec7fd (diff) | |
download | gcc-19aa3900bca808b49417a7aef295b5f1a583c298.zip gcc-19aa3900bca808b49417a7aef295b5f1a583c298.tar.gz gcc-19aa3900bca808b49417a7aef295b5f1a583c298.tar.bz2 |
MIPS: Add pattern for clo
gcc/ChangeLog:
* config/mips/mips.md (*clo<mode>2): New pattern.
gcc/testsuite/ChangeLog:
* gcc.target/mips/clz.c: New test.
* gcc.target/mips/clo.c: New test.
* gcc.target/mips/mips.exp: New option HAS_CLZ.
Signed-off-by: Junxian Zhu <zhujunxian@oss.cipunited.com>
-rw-r--r-- | gcc/config/mips/mips.md | 9 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/mips/clo.c | 11 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/mips/clz.c | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/mips/mips.exp | 3 |
4 files changed, 33 insertions, 0 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index f881a8b..ac1d77a 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3166,6 +3166,15 @@ [(set_attr "type" "clz") (set_attr "mode" "<MODE>")]) + +(define_insn "*clo<mode>2" + [(set (match_operand:GPR 0 "register_operand" "=d") + (clz:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))))] + "ISA_HAS_CLZ_CLO" + "<d>clo\t%0,%1" + [(set_attr "type" "clz") + (set_attr "mode" "<MODE>")]) + ;; ;; ................... ;; diff --git a/gcc/testsuite/gcc.target/mips/clo.c b/gcc/testsuite/gcc.target/mips/clo.c new file mode 100644 index 0000000..91f29a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/clo.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "(HAS_CLZ)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 unsigned int foo(unsigned int x) +{ + return __builtin_clz (~x); +} + +/* { dg-final { scan-assembler-not "\tclz\t" } } */ +/* { dg-final { scan-assembler "\tclo\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/clz.c b/gcc/testsuite/gcc.target/mips/clz.c new file mode 100644 index 0000000..74e6edb --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/clz.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "(HAS_CLZ)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 unsigned int foo(unsigned int x) +{ + return __builtin_clz (x); +} + +/* { dg-final { scan-assembler "\tclz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.target/mips/mips.exp index 025fbe7..ac3ab12 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -252,6 +252,7 @@ set mips_option_groups { warnings "-w" dump "-fdump-.*" ins "HAS_INS" + clz "HAS_CLZ" dmul "NOT_HAS_DMUL" ldc "HAS_LDC" movn "HAS_MOVN" @@ -1198,11 +1199,13 @@ proc mips-dg-options { args } { # # - paired-single instructions(*) # - odd numbered single precision registers + # - clz clo instructions # # (*) Note that we don't support MIPS V at the moment. } elseif { $isa_rev < 1 && ([mips_have_test_option_p options "-mpaired-single"] || ([mips_have_test_option_p options "-modd-spreg"] + || [mips_have_test_option_p options "HAS_CLZ"] && ![mips_have_test_option_p options "-mfp64"]))} { if { $gp_size == 32 } { mips_make_test_option options "-mips32" |