diff options
| author | Jim Wilson <wilson@gcc.gnu.org> | 1996-02-09 16:05:30 -0800 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1996-02-09 16:05:30 -0800 |
| commit | 197b2bf341b95bf0c33f82c759654cb1db63d19e (patch) | |
| tree | 0931a70ed8583b9653a5801704025eda31f40913 | |
| parent | 2ae0f82c69d39ceb76014746b43e9297c1bc2b6d (diff) | |
| download | gcc-197b2bf341b95bf0c33f82c759654cb1db63d19e.zip gcc-197b2bf341b95bf0c33f82c759654cb1db63d19e.tar.gz gcc-197b2bf341b95bf0c33f82c759654cb1db63d19e.tar.bz2 | |
(probe+2, probe+4): New conditional move patterns.
(movsicc): Don't truncate comparison if it is DImode.
From-SVN: r11191
| -rw-r--r-- | gcc/config/mips/mips.md | 39 |
1 files changed, 32 insertions, 7 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 23e35a3..ead8cdc 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -6480,6 +6480,21 @@ move\\t%0,%z4\\n\\ (define_insn "" [(set (match_operand:SI 0 "register_operand" "=d,d") (if_then_else:SI + (match_operator 4 "equality_op" + [(match_operand:DI 1 "register_operand" "d,d") + (const_int 0)]) + (match_operand:SI 2 "reg_or_0_operand" "dJ,0") + (match_operand:SI 3 "reg_or_0_operand" "0,dJ")))] + "mips_isa >= 4" + "@ + mov%B4\\t%0,%z2,%1 + mov%b4\\t%0,%z3,%1" + [(set_attr "type" "move") + (set_attr "mode" "SI")]) + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (if_then_else:SI (match_operator 3 "equality_op" [(reg:CC_FP 67) (const_int 0)]) (match_operand:SI 1 "reg_or_0_operand" "dJ,0") (match_operand:SI 2 "reg_or_0_operand" "0,dJ")))] @@ -6494,6 +6509,21 @@ move\\t%0,%z4\\n\\ [(set (match_operand:DI 0 "register_operand" "=d,d") (if_then_else:DI (match_operator 4 "equality_op" + [(match_operand:SI 1 "register_operand" "d,d") + (const_int 0)]) + (match_operand:DI 2 "reg_or_0_operand" "dJ,0") + (match_operand:DI 3 "reg_or_0_operand" "0,dJ")))] + "mips_isa >= 4" + "@ + mov%B4\\t%0,%z2,%1 + mov%b4\\t%0,%z3,%1" + [(set_attr "type" "move") + (set_attr "mode" "DI")]) + +(define_insn "" + [(set (match_operand:DI 0 "register_operand" "=d,d") + (if_then_else:DI + (match_operator 4 "equality_op" [(match_operand:DI 1 "register_operand" "d,d") (const_int 0)]) (match_operand:DI 2 "reg_or_0_operand" "dJ,0") @@ -6661,13 +6691,8 @@ move\\t%0,%z4\\n\\ operands[4] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM); } - if (mode == DImode) - operands[5] = gen_rtx (move_code, VOIDmode, - gen_lowpart (SImode, operands[4]), - CONST0_RTX (SImode)); - else - operands[5] = gen_rtx (move_code, VOIDmode, operands[4], - CONST0_RTX (SImode)); + operands[5] = gen_rtx (move_code, VOIDmode, operands[4], + CONST0_RTX (SImode)); }") ;; ??? Need movdicc, movsfcc, and movdfcc patterns. They should be |