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| author | Uros Bizjak <ubizjak@gmail.com> | 2024-02-27 18:41:24 +0100 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2024-02-27 18:41:24 +0100 |
| commit | 15d1dae0d4d1be88d28ad7578a60fd3e36de36d8 (patch) | |
| tree | 69c922dae5eccf1c932c0d0ec9222620ab82854c | |
| parent | 27534e793e51560213cef999df66a7214ee7502a (diff) | |
| download | gcc-15d1dae0d4d1be88d28ad7578a60fd3e36de36d8.zip gcc-15d1dae0d4d1be88d28ad7578a60fd3e36de36d8.tar.gz gcc-15d1dae0d4d1be88d28ad7578a60fd3e36de36d8.tar.bz2 | |
i386: psrlq is not used for PERM<a,{0},1,2,3,4> [PR113871]
Also handle V2BF mode.
PR target/113871
gcc/ChangeLog:
* config/i386/mmx.md (V248FI): Add V2BF mode.
(V24FI_32): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr113871-5a.c: New test.
* gcc.target/i386/pr113871-5b.c: New test.
| -rw-r--r-- | gcc/config/i386/mmx.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr113871-5a.c | 19 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr113871-5b.c | 19 |
3 files changed, 40 insertions, 2 deletions
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 075309c..2856ae6 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -85,9 +85,9 @@ (define_mode_iterator V24FI [V2SF V2SI V4HF V4HI]) -(define_mode_iterator V248FI [V2SF V2SI V4HF V4HI V8QI]) +(define_mode_iterator V248FI [V2SF V2SI V4HF V4BF V4HI V8QI]) -(define_mode_iterator V24FI_32 [V2HF V2HI V4QI]) +(define_mode_iterator V24FI_32 [V2HF V2BF V2HI V4QI]) ;; Mapping from integer vector mode to mnemonic suffix (define_mode_attr mmxvecsize diff --git a/gcc/testsuite/gcc.target/i386/pr113871-5a.c b/gcc/testsuite/gcc.target/i386/pr113871-5a.c new file mode 100644 index 0000000..25ab82a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113871-5a.c @@ -0,0 +1,19 @@ +/* PR target/113871 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ + +typedef __bf16 vect64 __attribute__((vector_size(8))); + +void f (vect64 *a) +{ + *a = __builtin_shufflevector(*a, (vect64){0}, 1, 2, 3, 4); +} + +/* { dg-final { scan-assembler "psrlq" } } */ + +void g(vect64 *a) +{ + *a = __builtin_shufflevector((vect64){0}, *a, 3, 4, 5, 6); +} + +/* { dg-final { scan-assembler "psllq" } } */ diff --git a/gcc/testsuite/gcc.target/i386/pr113871-5b.c b/gcc/testsuite/gcc.target/i386/pr113871-5b.c new file mode 100644 index 0000000..363a0f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113871-5b.c @@ -0,0 +1,19 @@ +/* PR target/113871 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ + +typedef __bf16 vect32 __attribute__((vector_size(4))); + +void f (vect32 *a) +{ + *a = __builtin_shufflevector(*a, (vect32){0}, 1, 2); +} + +/* { dg-final { scan-assembler "psrld" } } */ + +void g(vect32 *a) +{ + *a = __builtin_shufflevector((vect32){0}, *a, 1, 2); +} + +/* { dg-final { scan-assembler "pslld" } } */ |