rs6000-builtin.def (BU_FLOAT128_1_HW): New macros to support float128 built-in functions that require the ISA 3.0 hardware.

[gcc]
2017-09-14  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000-builtin.def (BU_FLOAT128_1_HW): New macros
	to support float128 built-in functions that require the ISA 3.0
	hardware.
	(BU_FLOAT128_3_HW): Likewise.
	(SQRTF128): Add support for the IEEE 128-bit square root and fma
	built-in functions.
	(FMAF128): Likewise.
	(FMAQ): Likewise.
	* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
	support for built-in functions that need the ISA 3.0 IEEE 128-bit
	floating point instructions.
	(rs6000_invalid_builtin): Likewise.
	(rs6000_builtin_mask_names): Likewise.
	* config/rs6000/rs6000.h (MASK_FLOAT128_HW): Likewise.
	(RS6000_BTM_FLOAT128_HW): Likewise.
	(RS6000_BTM_COMMON): Likewise.
	* config/rs6000/rs6000.md (fma<mode>4_hw): Add a generator
	function.
	* doc/extend.texi (RS/6000 built-in functions): Document the
	IEEE 128-bit floating point square root and fused multiply-add
	built-in functions.

[gcc/testsuite]
2017-09-14  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/abs128-1.c: Use __builtin_fabsf128 instead of
	__builtin_fabsq.
	* gcc.target/powerpc/float128-5.c: Use __builtin_fabsf128 instead
	of __builtin_fabsq.  Prevent the test from running on 32-bit.
	* gcc.target/powerpc/float128-fma1.c: New test.
	* gcc.target/powerpc/float128-fma2.c: Likewise.
	* gcc.target/powerpc/float128-sqrt1.c: Likewise.
	* gcc.target/powerpc/float128-sqrt2.c: Likewise.

From-SVN: r252771

9 files changed, 95 insertions, 11 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b66faeb..861616b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,27 @@
+2017-09-14  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* config/rs6000/rs6000-builtin.def (BU_FLOAT128_1_HW): New macros
+	to support float128 built-in functions that require the ISA 3.0
+	hardware.
+	(BU_FLOAT128_3_HW): Likewise.
+	(SQRTF128): Add support for the IEEE 128-bit square root and fma
+	built-in functions.
+	(FMAF128): Likewise.
+	(FMAQ): Likewise.
+	* config/rs6000/rs6000.c (rs6000_builtin_mask_calculate): Add
+	support for built-in functions that need the ISA 3.0 IEEE 128-bit
+	floating point instructions.
+	(rs6000_invalid_builtin): Likewise.
+	(rs6000_builtin_mask_names): Likewise.
+	* config/rs6000/rs6000.h (MASK_FLOAT128_HW): Likewise.
+	(RS6000_BTM_FLOAT128_HW): Likewise.
+	(RS6000_BTM_COMMON): Likewise.
+	* config/rs6000/rs6000.md (fma<mode>4_hw): Add a generator
+	function.
+	* doc/extend.texi (RS/6000 built-in functions): Document the
+	IEEE 128-bit floating point square root and fused multiply-add
+	built-in functions.
+
 2017-09-14  Pat Haugen  <pthaugen@us.ibm.com>
 
 	* config/rs6000/rs6000.c (rs6000_set_up_by_prologue): Make sure the TOC
diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index 18db576..07925b3 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -667,6 +667,23 @@
 		     | RS6000_BTC_UNARY),                               \
 		    CODE_FOR_ ## ICODE)                 /* ICODE */
 
+/* IEEE 128-bit floating-point builtins that need the ISA 3.0 hardware.  */
+#define BU_FLOAT128_1_HW(ENUM, NAME, ATTR, ICODE)                       \
+  RS6000_BUILTIN_1 (MISC_BUILTIN_ ## ENUM,              /* ENUM */      \
+		    "__builtin_" NAME,                  /* NAME */      \
+		    RS6000_BTM_FLOAT128_HW,             /* MASK */      \
+		    (RS6000_BTC_ ## ATTR                /* ATTR */      \
+		     | RS6000_BTC_UNARY),                               \
+		    CODE_FOR_ ## ICODE)                 /* ICODE */
+
+#define BU_FLOAT128_3_HW(ENUM, NAME, ATTR, ICODE)                       \
+  RS6000_BUILTIN_3 (MISC_BUILTIN_ ## ENUM,              /* ENUM */      \
+		    "__builtin_" NAME,                  /* NAME */      \
+		    RS6000_BTM_FLOAT128_HW,             /* MASK */      \
+		    (RS6000_BTC_ ## ATTR                /* ATTR */      \
+		     | RS6000_BTC_TERNARY),                             \
+		    CODE_FOR_ ## ICODE)                 /* ICODE */
+
 /* Miscellaneous builtins for instructions added in ISA 3.0.  These
    instructions don't require either the DFP or VSX options, just the basic
    ISA 3.0 enablement since they operate on general purpose registers.  */
@@ -2323,11 +2340,18 @@ BU_P9_OVERLOAD_2 (CMPRB,	"byte_in_range")
 BU_P9_OVERLOAD_2 (CMPRB2,	"byte_in_either_range")
 BU_P9_OVERLOAD_2 (CMPEQB,	"byte_in_set")
 
-/* 1 argument IEEE 128-bit floating-point functions.  */
+/* 1 and 2 argument IEEE 128-bit floating-point functions.  These functions use
+   the older 'q' suffix from libquadmath.  The standard built-in functions
+   support fabsf128 and copysignf128, but older code used these 'q' versions,
+   so keep them around.  */
 BU_FLOAT128_1 (FABSQ,		"fabsq",       CONST, abskf2)
-
-/* 2 argument IEEE 128-bit floating-point functions.  */
 BU_FLOAT128_2 (COPYSIGNQ,	"copysignq",   CONST, copysignkf3)
+
+/* 1 and 3 argument IEEE 128-bit floating point functions that require ISA 3.0
+   hardware.  These functions use the new 'f128' suffix.  Eventually these
+   should be folded into the common built-in function handling. */
+BU_FLOAT128_1_HW (SQRTF128,	"sqrtf128",	CONST, sqrtkf2)
+BU_FLOAT128_3_HW (FMAF128,	"fmaf128",	CONST, fmakf4_hw)
 
 /* 1 argument crypto functions.  */
 BU_CRYPTO_1 (VSBOX,		"vsbox",	  CONST, crypto_vsbox)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 6dd726e..005366b 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -3903,7 +3903,8 @@ rs6000_builtin_mask_calculate (void)
 	  | ((TARGET_DFP)		    ? RS6000_BTM_DFP	   : 0)
 	  | ((TARGET_HARD_FLOAT)	    ? RS6000_BTM_HARD_FLOAT : 0)
 	  | ((TARGET_LONG_DOUBLE_128)	    ? RS6000_BTM_LDBL128   : 0)
-	  | ((TARGET_FLOAT128_TYPE)	    ? RS6000_BTM_FLOAT128  : 0));
+	  | ((TARGET_FLOAT128_TYPE)	    ? RS6000_BTM_FLOAT128  : 0)
+	  | ((TARGET_FLOAT128_HW)	    ? RS6000_BTM_FLOAT128_HW : 0));
 }
 
 /* Implement TARGET_MD_ASM_ADJUST.  All asm statements are considered
@@ -16107,6 +16108,9 @@ rs6000_invalid_builtin (enum rs6000_builtins fncode)
   else if ((fnmask & RS6000_BTM_HARD_FLOAT) != 0)
     error ("builtin function %qs requires the %qs option", name,
 	   "-mhard-float");
+  else if ((fnmask & RS6000_BTM_FLOAT128_HW) != 0)
+    error ("builtin function %qs requires ISA 3.0 IEEE 128-bit floating point",
+	   name);
   else if ((fnmask & RS6000_BTM_FLOAT128) != 0)
     error ("builtin function %qs requires the %qs option", name, "-mfloat128");
   else
@@ -36227,6 +36231,7 @@ static struct rs6000_opt_mask const rs6000_builtin_mask_names[] =
   { "hard-float",	 RS6000_BTM_HARD_FLOAT,	false, false },
   { "long-double-128",	 RS6000_BTM_LDBL128,	false, false },
   { "float128",		 RS6000_BTM_FLOAT128,   false, false },
+  { "float128-hw",	 RS6000_BTM_FLOAT128_HW,false, false },
 };
 
 /* Option variables that we want to support inside attribute((target)) and
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 8ec192e..edd6971 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -640,6 +640,7 @@ extern int rs6000_vector_align[];
 #define MASK_DLMZB			OPTION_MASK_DLMZB
 #define MASK_EABI			OPTION_MASK_EABI
 #define MASK_FLOAT128_KEYWORD		OPTION_MASK_FLOAT128_KEYWORD
+#define MASK_FLOAT128_HW		OPTION_MASK_FLOAT128_HW
 #define MASK_FPRND			OPTION_MASK_FPRND
 #define MASK_P8_FUSION			OPTION_MASK_P8_FUSION
 #define MASK_HARD_FLOAT			OPTION_MASK_HARD_FLOAT
@@ -2499,6 +2500,7 @@ extern int frame_pointer_needed;
 #define RS6000_BTM_LDBL128	MASK_MULTIPLE	/* 128-bit long double.  */
 #define RS6000_BTM_64BIT	MASK_64BIT	/* 64-bit addressing.  */
 #define RS6000_BTM_FLOAT128	MASK_FLOAT128_KEYWORD /* IEEE 128-bit float.  */
+#define RS6000_BTM_FLOAT128_HW	MASK_FLOAT128_HW /* IEEE 128-bit float h/w.  */
 
 #define RS6000_BTM_COMMON	(RS6000_BTM_ALTIVEC			\
 				 | RS6000_BTM_VSX			\
@@ -2517,7 +2519,8 @@ extern int frame_pointer_needed;
 				 | RS6000_BTM_DFP			\
 				 | RS6000_BTM_HARD_FLOAT		\
 				 | RS6000_BTM_LDBL128			\
-				 | RS6000_BTM_FLOAT128)
+				 | RS6000_BTM_FLOAT128			\
+				 | RS6000_BTM_FLOAT128_HW)
 
 /* Define builtin enum index.  */
 
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 20873ac..7f17628 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -14316,7 +14316,7 @@
    (set_attr "size" "128")])
 
 ;; Initially don't worry about doing fusion
-(define_insn "*fma<mode>4_hw"
+(define_insn "fma<mode>4_hw"
   [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v")
 	(fma:IEEE128
 	 (match_operand:IEEE128 1 "altivec_register_operand" "%v")
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index cd5733e..499a3db 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -15339,6 +15339,21 @@ Similar to @code{__builtin_nans}, except the return type is @code{__float128}.
 @findex __builtin_nansq
 @end table
 
+The following built-in functions are available on Linux 64-bit systems
+that use the ISA 3.0 instruction set.
+
+@table @code
+@item __float128 __builtin_sqrtf128 (__float128)
+Similar to @code{__builtin_sqrtf}, except the return and input types
+are @code{__float128}.
+@findex __builtin_sqrtf128
+
+@item __float128 __builtin_fmaf128 (__float128, __float128, __float128)
+Similar to @code{__builtin_fma}, except the return and input types are
+@code{__float128}.
+@findex __builtin_fmaf128
+@end table
+
 The following built-in functions are available for the PowerPC family
 of processors, starting with ISA 2.05 or later (@option{-mcpu=power6}
 or @option{-mcmpb}):
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c03547b..b6d0009 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,14 @@
+2017-09-14  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+	* gcc.target/powerpc/abs128-1.c: Use __builtin_fabsf128 instead of
+	__builtin_fabsq.
+	* gcc.target/powerpc/float128-5.c: Use __builtin_fabsf128 instead
+	of __builtin_fabsq.  Prevent the test from running on 32-bit.
+	* gcc.target/powerpc/float128-fma1.c: New test.
+	* gcc.target/powerpc/float128-fma2.c: Likewise.
+	* gcc.target/powerpc/float128-sqrt1.c: Likewise.
+	* gcc.target/powerpc/float128-sqrt2.c: Likewise.
+
 2017-09-14  David Malcolm  <dmalcolm@redhat.com>
 
 	PR jit/82174
diff --git a/gcc/testsuite/gcc.target/powerpc/abs128-1.c b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
index 49635df..fe5206d 100644
--- a/gcc/testsuite/gcc.target/powerpc/abs128-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/abs128-1.c
@@ -39,7 +39,7 @@ main (int argc, int *argv[])
   x.nan.mant_high = 0x1234;
   x.nan.mant_low = 0xabcdef;
 
-  z.value = __builtin_fabsq (x.value);
+  z.value = __builtin_fabsf128 (x.value);
 
   if (z.nan.negative != 0
       || z.nan.exponent != 0x22
@@ -48,7 +48,7 @@ main (int argc, int *argv[])
       || z.nan.mant_low != 0xabcdef)
     abort ();
 
-  z.value = __builtin_fabsq (z.value);
+  z.value = __builtin_fabsf128 (z.value);
 
   if (z.nan.negative != 0
       || z.nan.exponent != 0x22
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-5.c b/gcc/testsuite/gcc.target/powerpc/float128-5.c
index f3cfee9..17f2fb2 100644
--- a/gcc/testsuite/gcc.target/powerpc/float128-5.c
+++ b/gcc/testsuite/gcc.target/powerpc/float128-5.c
@@ -1,9 +1,11 @@
-/* { dg-do compile { target { powerpc*-*-linux* } } } */
+/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */
 /* { dg-require-effective-target powerpc_p9vector_ok } */
 /* { dg-options "-O2 -mpower9-vector -mno-float128" } */
 
 /* Test that we can use #pragma GCC target to enable -mfloat128 and generate
-   code on ISA 3.0 for the float128 built-in functions.  */
+   code on ISA 3.0 for the float128 built-in functions.  Lp64 is required
+   because we need TImode to be available to enable __float128 using hardware
+   instructions.  */
 
 #ifdef __FLOAT128__
 #error "-mno-float128 should disable initially defining __FLOAT128__"
@@ -18,7 +20,7 @@
 __float128
 qabs (__float128 a)
 {
-  return __builtin_fabsq (a);
+  return __builtin_fabsf128 (a);
 }
 
 /* { dg-final { scan-assembler "xsabsqp"  } } */