RISC-V: Add vnmsac vx C++ api tests

gcc/testsuite/ChangeLog:

	* g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.C: New test.
	* g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.C: New test.

15 files changed, 5184 insertions, 0 deletions

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.C
new file mode 100644
index 0000000..b90dc04
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.C
new file mode 100644
index 0000000..2908cdb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.C
new file mode 100644
index 0000000..43c7026
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_mu_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_mu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_mu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_mu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_mu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_mu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_mu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_mu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_mu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_mu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_mu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_mu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_mu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_mu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_mu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_mu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_mu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_mu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_mu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_mu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_mu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_mu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-1.C
new file mode 100644
index 0000000..5079058
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-1.C
@@ -0,0 +1,572 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,vl);
+}
+
+
+vint8mf8_t test___riscv_vnmsac(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-2.C
new file mode 100644
index 0000000..ee50714
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-2.C
@@ -0,0 +1,572 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,31);
+}
+
+
+vint8mf8_t test___riscv_vnmsac(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-3.C
new file mode 100644
index 0000000..0ef1763
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_rv32-3.C
@@ -0,0 +1,572 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(vd,rs1,vs2,32);
+}
+
+
+vint8mf8_t test___riscv_vnmsac(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.C
new file mode 100644
index 0000000..faadb19
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.C
new file mode 100644
index 0000000..01c377d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.C
new file mode 100644
index 0000000..c6fb0cf
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tu_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tu(vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tu(vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tu(vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tu(vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tu(vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tu(vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tu(vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tu(vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tu(vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tu(vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tu(vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tu(vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tu(vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tu(vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tu(vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tu(vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tu(vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tu(vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tu(vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tu(vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tu(vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tu(vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tu(vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tu(vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tu(vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tu(vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tu(vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tu(vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tu(vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tu(vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tu(vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tu(vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tu(vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tu(vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tu(vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tu(vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tu(vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tu(vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tu(vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tu(vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tu(vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tu(vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tu(vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tu(vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tu(vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.C
new file mode 100644
index 0000000..06247af
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.C
new file mode 100644
index 0000000..5aa24c5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.C
new file mode 100644
index 0000000..65c25c5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tum_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tum(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tum(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tum(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tum(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tum(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tum(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tum(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tum(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tum(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tum(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tum(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tum(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tum(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tum(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tum(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tum(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tum(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tum(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tum(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tum(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tum(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.C
new file mode 100644
index 0000000..eab3109
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.C
new file mode 100644
index 0000000..c8b2dfa
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.C
new file mode 100644
index 0000000..fc484ef
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnmsac_vx_tumu_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vint8mf8_t vd,int8_t rs1,vint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vint8mf4_t vd,int8_t rs1,vint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint8mf2_t vd,int8_t rs1,vint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vint8m1_t vd,int8_t rs1,vint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vint8m2_t vd,int8_t rs1,vint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vint8m4_t vd,int8_t rs1,vint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vint8m8_t vd,int8_t rs1,vint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vint16mf4_t vd,int16_t rs1,vint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint16mf2_t vd,int16_t rs1,vint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vint16m1_t vd,int16_t rs1,vint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vint16m2_t vd,int16_t rs1,vint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vint16m4_t vd,int16_t rs1,vint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vint16m8_t vd,int16_t rs1,vint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vint32mf2_t vd,int32_t rs1,vint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vint32m1_t vd,int32_t rs1,vint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vint32m2_t vd,int32_t rs1,vint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vint32m4_t vd,int32_t rs1,vint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vint32m8_t vd,int32_t rs1,vint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vint64m1_t vd,int64_t rs1,vint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vint64m2_t vd,int64_t rs1,vint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vint64m4_t vd,int64_t rs1,vint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vint64m8_t vd,int64_t rs1,vint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf8_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint8mf8_t vd,uint8_t rs1,vuint8mf8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf4_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint8mf4_t vd,uint8_t rs1,vuint8mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8mf2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint8mf2_t vd,uint8_t rs1,vuint8mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m1_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint8m1_t vd,uint8_t rs1,vuint8m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m2_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint8m2_t vd,uint8_t rs1,vuint8m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m4_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint8m4_t vd,uint8_t rs1,vuint8m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint8m8_t test___riscv_vnmsac_tumu(vbool1_t mask,vuint8m8_t vd,uint8_t rs1,vuint8m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf4_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint16mf4_t vd,uint16_t rs1,vuint16mf4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16mf2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint16mf2_t vd,uint16_t rs1,vuint16mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m1_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint16m1_t vd,uint16_t rs1,vuint16m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m2_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint16m2_t vd,uint16_t rs1,vuint16m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m4_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint16m4_t vd,uint16_t rs1,vuint16m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint16m8_t test___riscv_vnmsac_tumu(vbool2_t mask,vuint16m8_t vd,uint16_t rs1,vuint16m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32mf2_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint32mf2_t vd,uint32_t rs1,vuint32mf2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m1_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint32m1_t vd,uint32_t rs1,vuint32m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m2_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint32m2_t vd,uint32_t rs1,vuint32m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m4_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint32m4_t vd,uint32_t rs1,vuint32m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint32m8_t test___riscv_vnmsac_tumu(vbool4_t mask,vuint32m8_t vd,uint32_t rs1,vuint32m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m1_t test___riscv_vnmsac_tumu(vbool64_t mask,vuint64m1_t vd,uint64_t rs1,vuint64m1_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m2_t test___riscv_vnmsac_tumu(vbool32_t mask,vuint64m2_t vd,uint64_t rs1,vuint64m2_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m4_t test___riscv_vnmsac_tumu(vbool16_t mask,vuint64m4_t vd,uint64_t rs1,vuint64m4_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+vuint64m8_t test___riscv_vnmsac_tumu(vbool8_t mask,vuint64m8_t vd,uint64_t rs1,vuint64m8_t vs2,size_t vl)
+{
+    return __riscv_vnmsac_tumu(mask,vd,rs1,vs2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnms[a-u][b-c]\.vx\s+v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vnms[a-u][b-c]\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */