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| author | John David Anglin <danglin@gcc.gnu.org> | 2023-09-29 15:37:44 +0000 |
|---|---|---|
| committer | John David Anglin <danglin@gcc.gnu.org> | 2023-09-29 15:39:51 +0000 |
| commit | 0f184b4141e9d285c19b3a3d02bffa45bc0d8f07 (patch) | |
| tree | 4de8000ee55ea060436c620b6e4d65acb6fc1f92 | |
| parent | a8b9c32da787ea0bfbfc9118ac816fa7be4b1bc8 (diff) | |
| download | gcc-0f184b4141e9d285c19b3a3d02bffa45bc0d8f07.zip gcc-0f184b4141e9d285c19b3a3d02bffa45bc0d8f07.tar.gz gcc-0f184b4141e9d285c19b3a3d02bffa45bc0d8f07.tar.bz2 | |
Fix memory barrier patterns for pre PA8800 processors
2023-09-29 John David Anglin <danglin@gcc.gnu.org>
* config/pa/pa.md (memory_barrier): Revise comment.
(memory_barrier_64, memory_barrier_32): Use ldcw,co on PA 2.0.
* config/pa/pa.opt (coherent-ldcw): Change default to disabled.
| -rw-r--r-- | gcc/config/pa/pa.md | 12 | ||||
| -rw-r--r-- | gcc/config/pa/pa.opt | 2 |
2 files changed, 7 insertions, 7 deletions
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index f603591..4f85991 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -10739,10 +10739,10 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" ;; generating PA 1.x code even though all PA 1.x systems are strongly ordered. ;; When barriers are needed, we use a strongly ordered ldcw instruction as -;; the barrier. Most PA 2.0 targets are cache coherent. In that case, we -;; can use the coherent cache control hint and avoid aligning the ldcw -;; address. In spite of its description, it is not clear that the sync -;; instruction works as a barrier. +;; the barrier. All PA 2.0 targets accept the "co" cache control hint but +;; only PA8800 and PA8900 processors implement the cacheable hint. In +;; that case, we can avoid aligning the ldcw address. In spite of its +;; description, it is not clear that the sync instruction works as a barrier. (define_expand "memory_barrier" [(parallel @@ -10772,7 +10772,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (clobber (match_operand 1 "pmode_register_operand" "=&r"))] "TARGET_64BIT" - "ldo 15(%%sp),%1\n\tdepd %%r0,63,3,%1\n\tldcw 0(%1),%1" + "ldo 15(%%sp),%1\n\tdepd %%r0,63,3,%1\n\tldcw,co 0(%1),%1" [(set_attr "type" "binary") (set_attr "length" "12")]) @@ -10781,6 +10781,6 @@ add,l %2,%3,%3\;bv,n %%r0(%3)" (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (clobber (match_operand 1 "pmode_register_operand" "=&r"))] "" - "ldo 15(%%sp),%1\n\t{dep|depw} %%r0,31,3,%1\n\tldcw 0(%1),%1" + "ldo 15(%%sp),%1\n\t{dep|depw} %%r0,31,3,%1\n\t{ldcw|ldcw,co} 0(%1),%1" [(set_attr "type" "binary") (set_attr "length" "12")]) diff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt index dd358f2..573edce 100644 --- a/gcc/config/pa/pa.opt +++ b/gcc/config/pa/pa.opt @@ -50,7 +50,7 @@ Target Mask(CALLER_COPIES) Caller copies function arguments passed by hidden reference. mcoherent-ldcw -Target Var(TARGET_COHERENT_LDCW) Init(1) +Target Var(TARGET_COHERENT_LDCW) Init(0) Use ldcw/ldcd coherent cache-control hint. mdisable-fpregs |