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| author | liuhongt <hongtao.liu@intel.com> | 2023-08-09 14:25:53 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2023-08-10 14:06:18 +0800 |
| commit | 0c563a935c47e507ad97e15860ac017c14877b31 (patch) | |
| tree | e9be3633fd123b991c59ff3b0142f2ec66e6ca07 | |
| parent | 4cede0de9a19ee1a911b27dbe0916e67f1f3d7c9 (diff) | |
| download | gcc-0c563a935c47e507ad97e15860ac017c14877b31.zip gcc-0c563a935c47e507ad97e15860ac017c14877b31.tar.gz gcc-0c563a935c47e507ad97e15860ac017c14877b31.tar.bz2 | |
i386: Do not sanitize upper part of V2HFmode and V4HFmode reg with -fno-trapping-math [PR110832]
Also add ix86_partial_vec_fp_math to to condition of V2HF/V4HF named
patterns in order to avoid generation of partial vector V8HFmode
trapping instructions.
gcc/ChangeLog:
PR target/110832
* config/i386/mmx.md: (movq_<mode>_to_sse): Also do not
sanitize upper part of V4HFmode register with
-fno-trapping-math.
(<insn>v4hf3): Enable for ix86_partial_vec_fp_math.
(<divv4hf3): Ditto.
(<insn>v2hf3): Ditto.
(divv2hf3): Ditto.
(movd_v2hf_to_sse): Do not sanitize upper part of V2HFmode
register with -fno-trapping-math.
| -rw-r--r-- | gcc/config/i386/mmx.md | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index d51b3b9..170432a 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -596,7 +596,7 @@ (match_dup 2)))] "TARGET_SSE2" { - if (<MODE>mode == V2SFmode + if (<MODE>mode != V2SImode && !flag_trapping_math) { rtx op1 = force_reg (<MODE>mode, operands[1]); @@ -1941,7 +1941,7 @@ (plusminusmult:V4HF (match_operand:V4HF 1 "nonimmediate_operand") (match_operand:V4HF 2 "nonimmediate_operand")))] - "TARGET_AVX512FP16 && TARGET_AVX512VL" + "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" { rtx op2 = gen_reg_rtx (V8HFmode); rtx op1 = gen_reg_rtx (V8HFmode); @@ -1961,7 +1961,7 @@ (div:V4HF (match_operand:V4HF 1 "nonimmediate_operand") (match_operand:V4HF 2 "nonimmediate_operand")))] - "TARGET_AVX512FP16 && TARGET_AVX512VL" + "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" { rtx op2 = gen_reg_rtx (V8HFmode); rtx op1 = gen_reg_rtx (V8HFmode); @@ -1983,14 +1983,22 @@ (match_operand:V2HF 1 "nonimmediate_operand")) (match_operand:V8HF 2 "reg_or_0_operand") (const_int 3)))] - "TARGET_SSE") + "TARGET_SSE" +{ + if (!flag_trapping_math && operands[2] == CONST0_RTX (V8HFmode)) + { + rtx op1 = force_reg (V2HFmode, operands[1]); + emit_move_insn (operands[0], lowpart_subreg (V8HFmode, op1, V2HFmode)); + DONE; + } +}) (define_expand "<insn>v2hf3" [(set (match_operand:V2HF 0 "register_operand") (plusminusmult:V2HF (match_operand:V2HF 1 "nonimmediate_operand") (match_operand:V2HF 2 "nonimmediate_operand")))] - "TARGET_AVX512FP16 && TARGET_AVX512VL" + "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" { rtx op2 = gen_reg_rtx (V8HFmode); rtx op1 = gen_reg_rtx (V8HFmode); @@ -2009,7 +2017,7 @@ (div:V2HF (match_operand:V2HF 1 "nonimmediate_operand") (match_operand:V2HF 2 "nonimmediate_operand")))] - "TARGET_AVX512FP16 && TARGET_AVX512VL" + "TARGET_AVX512FP16 && TARGET_AVX512VL && ix86_partial_vec_fp_math" { rtx op2 = gen_reg_rtx (V8HFmode); rtx op1 = gen_reg_rtx (V8HFmode); |