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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-12-25 14:19:52 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-12-25 14:36:44 +0800 |
| commit | 0beeddd6b1b1cb41104c4df925323e8fc0437ba8 (patch) | |
| tree | 2027c5d53a6d9348aa4029a3d46fb31f3f6baeac | |
| parent | 59ecd5ff096f800de17b804f1482055f2d84d629 (diff) | |
| download | gcc-0beeddd6b1b1cb41104c4df925323e8fc0437ba8.zip gcc-0beeddd6b1b1cb41104c4df925323e8fc0437ba8.tar.gz gcc-0beeddd6b1b1cb41104c4df925323e8fc0437ba8.tar.bz2 | |
RISC-V: Add one more ASM check in PR113112-1.c
gcc/testsuite/ChangeLog:
* gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c: Add one more ASM check.
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c index a44a1c0..31b41ba 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/pr113112-1.c @@ -20,6 +20,7 @@ foo (int n){ return 0; } +/* { dg-final { scan-assembler {e32,m4} } } */ /* { dg-final { scan-assembler-not {jr} } } */ /* { dg-final { scan-assembler-times {ret} 1 } } */ /* { dg-final { scan-tree-dump "Maximum lmul = 8" "vect" } } */ |