RISC-V: Introduce vfloat16m{f}*_t and their machine mode.

This patch would like to introduce the built-in type vfloat16m{f}*_t, as
well as their machine mode VNx*HF. They depend on architecture zvfhmin
or zvfh.

When givn the zvfhmin or zvfh, the macro TARGET_VECTOR_ELEN_FP_16 will
be true.

The underlying PATCH will implement the zvfhmin extension based on this.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* common/config/riscv/riscv-common.cc: Add FP_16 mask to zvfhmin
	and zvfh.
	* config/riscv/genrvv-type-indexer.cc (valid_type): Allow FP16.
	(main): Disable FP16 tuple.
	* config/riscv/riscv-opts.h (MASK_VECTOR_ELEN_FP_16): New macro.
	(TARGET_VECTOR_ELEN_FP_16): Ditto.
	* config/riscv/riscv-vector-builtins.cc (check_required_extensions):
	Add FP16.
	* config/riscv/riscv-vector-builtins.def (vfloat16mf4_t): New type.
	(vfloat16mf2_t): Ditto.
	(vfloat16m1_t): Ditto.
	(vfloat16m2_t): Ditto.
	(vfloat16m4_t): Ditto.
	(vfloat16m8_t): Ditto.
	* config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_FP_16):
	New macro.
	* config/riscv/riscv-vector-switch.def (ENTRY): Allow FP16
	machine mode based on TARGET_VECTOR_ELEN_FP_16.

7 files changed, 49 insertions, 10 deletions

diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc
index e6ed3df..3247d52 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -1248,6 +1248,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zve64x",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
   {"zve64f",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_32},
   {"zve64d",   &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_64},
+  {"zvfhmin",  &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16},
+  {"zvfh",     &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_FP_16},
 
   {"zvl32b",    &gcc_options::x_riscv_zvl_flags, MASK_ZVL32B},
   {"zvl64b",    &gcc_options::x_riscv_zvl_flags, MASK_ZVL64B},
diff --git a/gcc/config/riscv/genrvv-type-indexer.cc b/gcc/config/riscv/genrvv-type-indexer.cc
index 18e1b37..8fc93ce 100644
--- a/gcc/config/riscv/genrvv-type-indexer.cc
+++ b/gcc/config/riscv/genrvv-type-indexer.cc
@@ -54,7 +54,7 @@ valid_type (unsigned sew, int lmul_log2, bool float_p)
     case 8:
       return lmul_log2 >= -3 && !float_p;
     case 16:
-      return lmul_log2 >= -2 && !float_p;
+      return lmul_log2 >= -2;
     case 32:
       return lmul_log2 >= -1;
     case 64:
@@ -73,6 +73,9 @@ valid_type (unsigned sew, int lmul_log2, unsigned nf, bool float_p)
   if (nf > 8 || nf < 1)
     return false;
 
+  if (sew == 16 && nf != 1 && float_p) // Disable FP16 tuple in temporarily.
+    return false;
+
   switch (lmul_log2)
     {
     case 1:
@@ -342,7 +345,7 @@ main (int argc, const char **argv)
 	    fprintf (fp, ")\n");
 	  }
   // Build for vfloat
-  for (unsigned sew : {32, 64})
+  for (unsigned sew : {16, 32, 64})
     for (int lmul_log2 : {-3, -2, -1, 0, 1, 2, 3})
       for (unsigned nf : {1, 2, 3, 4, 5, 6, 7, 8})
 	{
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 5f387d0..208a557 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -154,6 +154,8 @@ enum riscv_entity
 #define MASK_VECTOR_ELEN_64    (1 << 1)
 #define MASK_VECTOR_ELEN_FP_32 (1 << 2)
 #define MASK_VECTOR_ELEN_FP_64 (1 << 3)
+/* Align the bit index to riscv-vector-builtins.h.  */
+#define MASK_VECTOR_ELEN_FP_16 (1 << 6)
 
 #define TARGET_VECTOR_ELEN_32 \
   ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
@@ -163,6 +165,8 @@ enum riscv_entity
   ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
 #define TARGET_VECTOR_ELEN_FP_64 \
   ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
+#define TARGET_VECTOR_ELEN_FP_16 \
+  ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_16) != 0)
 
 #define MASK_ZVL32B    (1 <<  0)
 #define MASK_ZVL64B    (1 <<  1)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 9fea707..43bf6d8 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -2944,6 +2944,8 @@ check_required_extensions (const function_instance &instance)
 
   uint64_t riscv_isa_flags = 0;
 
+  if (TARGET_VECTOR_ELEN_FP_16)
+    riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_16;
   if (TARGET_VECTOR_ELEN_FP_32)
     riscv_isa_flags |= RVV_REQUIRE_ELEN_FP_32;
   if (TARGET_VECTOR_ELEN_FP_64)
diff --git a/gcc/config/riscv/riscv-vector-builtins.def b/gcc/config/riscv/riscv-vector-builtins.def
index 61346e5..149835f 100644
--- a/gcc/config/riscv/riscv-vector-builtins.def
+++ b/gcc/config/riscv/riscv-vector-builtins.def
@@ -490,6 +490,26 @@ DEF_RVV_TYPE (vint64m8_t, 15, __rvv_int64m8_t, int64, VNx16DI, VNx8DI, VOID, _i6
 DEF_RVV_TYPE (vuint64m8_t, 16, __rvv_uint64m8_t, uint64, VNx16DI, VNx8DI, VOID, _u64m8,
 	      _u64, _e64m8)
 
+/* Enabled if TARGET_VECTOR_ELEN_FP_16 && 9TARGET_ZVFH or TARGET_ZVFHMIN).  */
+/* LMUL = 1/4.  */
+DEF_RVV_TYPE (vfloat16mf4_t, 18, __rvv_float16mf4_t, float16, VNx2HF, VNx1HF, VOID,
+	      _f16mf4, _f16, _e16mf4)
+/* LMUL = 1/2.  */
+DEF_RVV_TYPE (vfloat16mf2_t, 18, __rvv_float16mf2_t, float16, VNx4HF, VNx2HF, VNx1HF,
+	      _f16mf2, _f16, _e16mf2)
+/* LMUL = 1.  */
+DEF_RVV_TYPE (vfloat16m1_t, 17, __rvv_float16m1_t, float16, VNx8HF, VNx4HF, VNx2HF,
+	      _f16m1, _f16, _e16m1)
+/* LMUL = 2.  */
+DEF_RVV_TYPE (vfloat16m2_t, 17, __rvv_float16m2_t, float16, VNx16HF, VNx8HF, VNx4HF,
+	      _f16m2, _f16, _e16m2)
+/* LMUL = 4.  */
+DEF_RVV_TYPE (vfloat16m4_t, 17, __rvv_float16m4_t, float16, VNx32HF, VNx16HF, VNx8HF,
+	      _f16m4, _f16, _e16m4)
+/* LMUL = 8.  */
+DEF_RVV_TYPE (vfloat16m8_t, 16, __rvv_float16m8_t, float16, VNx64HF, VNx32HF, VNx16HF,
+	      _f16m8, _f16, _e16m8)
+
 /* Disable all when !TARGET_VECTOR_ELEN_FP_32.  */
 /* LMUL = 1/2:
    Only enble when TARGET_MIN_VLEN > 32.
diff --git a/gcc/config/riscv/riscv-vector-builtins.h b/gcc/config/riscv/riscv-vector-builtins.h
index 5d43457..b0c3a42 100644
--- a/gcc/config/riscv/riscv-vector-builtins.h
+++ b/gcc/config/riscv/riscv-vector-builtins.h
@@ -108,6 +108,7 @@ static const unsigned int CP_WRITE_CSR = 1U << 5;
 #define RVV_REQUIRE_ELEN_FP_64 (1 << 3) /* Require FP ELEN >= 64.  */
 #define RVV_REQUIRE_FULL_V (1 << 4) /* Require Full 'V' extension.  */
 #define RVV_REQUIRE_MIN_VLEN_64 (1 << 5)	/* Require TARGET_MIN_VLEN >= 64.  */
+#define RVV_REQUIRE_ELEN_FP_16 (1 << 6) /* Require FP ELEN >= 32.  */
 
 /* Enumerates the RVV operand types.  */
 enum operand_type_index
diff --git a/gcc/config/riscv/riscv-vector-switch.def b/gcc/config/riscv/riscv-vector-switch.def
index 4b1c32d..52f07709 100644
--- a/gcc/config/riscv/riscv-vector-switch.def
+++ b/gcc/config/riscv/riscv-vector-switch.def
@@ -120,14 +120,21 @@ ENTRY (VNx4HI, true, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32)
 ENTRY (VNx2HI, true, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
 ENTRY (VNx1HI, TARGET_MIN_VLEN < 128, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
 
-/* TODO:Disable all FP16 vector, enable them when 'zvfh' is supported.  */
-ENTRY (VNx64HF, false, LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_8, 2)
-ENTRY (VNx32HF, false, LMUL_RESERVED, 0, LMUL_8, 2, LMUL_4, 4)
-ENTRY (VNx16HF, false, LMUL_8, 2, LMUL_4, 4, LMUL_2, 8)
-ENTRY (VNx8HF, false, LMUL_4, 4, LMUL_2, 8, LMUL_1, 16)
-ENTRY (VNx4HF, false, LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32)
-ENTRY (VNx2HF, false, LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
-ENTRY (VNx1HF, false, LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
+/* SEW = 16 for float point.  Enabled when 'zvfh' or 'zvfhmin' is given.  */
+ENTRY (VNx64HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128, \
+  LMUL_RESERVED, 0, LMUL_RESERVED, 0, LMUL_8, 2)
+ENTRY (VNx32HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32, \
+  LMUL_RESERVED, 0, LMUL_8, 2, LMUL_4, 4)
+ENTRY (VNx16HF, TARGET_VECTOR_ELEN_FP_16, \
+  LMUL_8, 2, LMUL_4, 4, LMUL_2, 8)
+ENTRY (VNx8HF, TARGET_VECTOR_ELEN_FP_16, \
+  LMUL_4, 4, LMUL_2, 8, LMUL_1, 16)
+ENTRY (VNx4HF, TARGET_VECTOR_ELEN_FP_16, \
+  LMUL_2, 8, LMUL_1, 16, LMUL_F2, 32)
+ENTRY (VNx2HF, TARGET_VECTOR_ELEN_FP_16, \
+  LMUL_1, 16, LMUL_F2, 32, LMUL_F4, 64)
+ENTRY (VNx1HF, TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN < 128, \
+  LMUL_F2, 32, LMUL_F4, 64, LMUL_RESERVED, 0)
 
 /* SEW = 32. Disable VNx16SImode when TARGET_MIN_VLEN == 32.
    For single-precision floating-point, we need TARGET_VECTOR_ELEN_FP_32 to be