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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2024-01-30 09:19:06 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-01-30 09:26:03 +0800 |
| commit | 0ac37563fa41c72e499abd620c652ba5debe7fb9 (patch) | |
| tree | 4a2eb8a2e18b4bcfc3e4f44fd13a829e908282bf | |
| parent | f07068197df6d4d7c63be209f4fb5a7ec99100dc (diff) | |
| download | gcc-0ac37563fa41c72e499abd620c652ba5debe7fb9.zip gcc-0ac37563fa41c72e499abd620c652ba5debe7fb9.tar.gz gcc-0ac37563fa41c72e499abd620c652ba5debe7fb9.tar.bz2 | |
RISC-V: Fix regression
Due to recent middle-end loop vectorizer changes, these tests have regression and
the changes are reasonable. Adapt test to fix the regression.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: Adapt test.
* gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/mod-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/shift-1.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/shift-2.c: Ditto.
5 files changed, 5 insertions, 5 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c index befa4b8..d534885 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c @@ -4,5 +4,5 @@ #include "shift-template.h" /* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsrl\.vv} 2 } } */ /* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c index 976b29f..a533dc7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c @@ -4,5 +4,5 @@ #include "shift-template.h" /* { dg-final { scan-assembler-times {\tvsll\.vv} 8 } } */ -/* { dg-final { scan-assembler-times {\tvsrl\.vv} 4 } } */ +/* { dg-final { scan-assembler-times {\tvsrl\.vv} 2 } } */ /* { dg-final { scan-assembler-times {\tvsra\.vv} 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c index 57bbf8f..17d2784 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mod-1.c @@ -53,5 +53,5 @@ DEF_OP_VV (mod, 128, int64_t, %) DEF_OP_VV (mod, 256, int64_t, %) DEF_OP_VV (mod, 512, int64_t, %) -/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ +/* { dg-final { scan-assembler-times {vremu?\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 47 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c index cb5a1db..ee8da25 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-1.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, int64_t, >>) DEF_OP_VV (shift, 256, int64_t, >>) DEF_OP_VV (shift, 512, int64_t, >>) -/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ +/* { dg-final { scan-assembler-times {vsra\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 35 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c index e626a52..ebd5575 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/shift-2.c @@ -53,5 +53,5 @@ DEF_OP_VV (shift, 128, uint64_t, >>) DEF_OP_VV (shift, 256, uint64_t, >>) DEF_OP_VV (shift, 512, uint64_t, >>) -/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 42 } } */ +/* { dg-final { scan-assembler-times {vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 19 } } */ /* { dg-final { scan-assembler-not {csrr} } } */ |