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| author | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2010-09-08 21:35:48 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana@gcc.gnu.org> | 2010-09-08 21:35:48 +0000 |
| commit | 0a7822a32b830084f37e78545047ce0d4e5cd486 (patch) | |
| tree | 2fb5bfd03faabf6ced00b003e9814012ff8f46b1 | |
| parent | 03dbada4fb1c4400d6dc73f18da479b7fb86530f (diff) | |
| download | gcc-0a7822a32b830084f37e78545047ce0d4e5cd486.zip gcc-0a7822a32b830084f37e78545047ce0d4e5cd486.tar.gz gcc-0a7822a32b830084f37e78545047ce0d4e5cd486.tar.bz2 | |
re PR target/44392 (libgcc compile with --enable-target-optspace (-Os) causes recursion in __bswapsi2)
2010-09-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/44392
* config/arm/arm.md (bswapsi2): Handle condition correctly
for armv6 and optimize_size.
From-SVN: r164029
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 43 |
2 files changed, 25 insertions, 24 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b909355..c121a35 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2010-09-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + PR target/44392 + * config/arm/arm.md (bswapsi2): Handle condition correctly + for armv6 and optimize_size. + 2010-09-08 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org> PR other/18555 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 9d98ca5..8806dc5 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10658,34 +10658,29 @@ (define_expand "bswapsi2" [(set (match_operand:SI 0 "s_register_operand" "=r") (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))] -"TARGET_EITHER" +"TARGET_EITHER && (arm_arch6 || !optimize_size)" " - if (!arm_arch6) - { - if (!optimize_size) - { - rtx op2 = gen_reg_rtx (SImode); - rtx op3 = gen_reg_rtx (SImode); + if (!arm_arch6) + { + rtx op2 = gen_reg_rtx (SImode); + rtx op3 = gen_reg_rtx (SImode); - if (TARGET_THUMB) - { - rtx op4 = gen_reg_rtx (SImode); - rtx op5 = gen_reg_rtx (SImode); + if (TARGET_THUMB) + { + rtx op4 = gen_reg_rtx (SImode); + rtx op5 = gen_reg_rtx (SImode); - emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], - op2, op3, op4, op5)); - } - else - { - emit_insn (gen_arm_legacy_rev (operands[0], operands[1], - op2, op3)); - } + emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], + op2, op3, op4, op5)); + } + else + { + emit_insn (gen_arm_legacy_rev (operands[0], operands[1], + op2, op3)); + } - DONE; - } - else - FAIL; - } + DONE; + } " ) |