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| author | Thomas Preud'homme <thomas.preudhomme@arm.com> | 2016-06-01 16:54:18 +0000 |
|---|---|---|
| committer | Thomas Preud'homme <thopre01@gcc.gnu.org> | 2016-06-01 16:54:18 +0000 |
| commit | 042dee3e3bd99807f894963d89177a0f0db6ffd5 (patch) | |
| tree | f6598610fe9728dcde7847d7f799875326f82b43 | |
| parent | 15c98b2e0d51511893baaf477beb496ed425bae8 (diff) | |
| download | gcc-042dee3e3bd99807f894963d89177a0f0db6ffd5.zip gcc-042dee3e3bd99807f894963d89177a0f0db6ffd5.tar.gz gcc-042dee3e3bd99807f894963d89177a0f0db6ffd5.tar.bz2 | |
sourcebuild.texi (arm_acq_rel): Document new effective target.
2016-06-01 Thomas Preud'homme <thomas.preudhomme@arm.com>
gcc/
* doc/sourcebuild.texi (arm_acq_rel): Document new effective target.
gcc/testsuite/
* lib/target-supports.exp (check_effective_target_arm_acq_rel): New
procedure.
From-SVN: r237002
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/doc/sourcebuild.texi | 3 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/lib/target-supports.exp | 23 |
4 files changed, 35 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 8eb0cd5..45ae2f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2016-06-01 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * doc/sourcebuild.texi (arm_acq_rel): Document new effective target. + 2016-06-01 Eduard Sanou <dhole@openmailbox.org> * doc/cppenv.texi: Note that the `%s` in `date` is a non-standard diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index 41657b5..0c03920 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -1597,6 +1597,9 @@ ARM target supports executing ARMv8.1 Adv.SIMD instructions. Some multilibs may be incompatible with the options needed. Implies arm_v8_1a_neon_ok. +@item arm_acq_rel +ARM target supports acquire-release instructions. + @item arm_prefer_ldrd_strd ARM target prefers @code{LDRD} and @code{STRD} instructions over @code{LDM} and @code{STM} instructions. diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 497a215..5bc6676 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-06-01 Thomas Preud'homme <thomas.preudhomme@arm.com> + + * lib/target-supports.exp (check_effective_target_arm_acq_rel): New + procedure. + 2016-06-01 Eduard Sanou <dhole@openmailbox.org> * gcc.dg/cpp/source_date_epoch-1.c: New file, test the proper diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 04ca176..f4cb276 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3494,6 +3494,25 @@ proc check_effective_target_arm_neonv2 { } { } } +# Return 1 if this is an ARM target with load acquire and store release +# instructions for 8-, 16- and 32-bit types. + +proc check_effective_target_arm_acq_rel { } { + return [check_no_compiler_messages arm_acq_rel object { + void + load_acquire_store_release (void) + { + asm ("lda r0, [r1]\n\t" + "stl r0, [r1]\n\t" + "ldah r0, [r1]\n\t" + "stlh r0, [r1]\n\t" + "ldab r0, [r1]\n\t" + "stlb r0, [r1]" + : : : "r0", "memory"); + } + }] +} + # Return 1 if this a Loongson-2E or -2F target using an ABI that supports # the Loongson vector modes. @@ -5725,6 +5744,8 @@ proc check_effective_target_sync_int_long { } { || [istarget aarch64*-*-*] || [istarget alpha*-*-*] || [istarget arm*-*-linux-*] + || ([istarget arm*-*-*] + && [check_effective_target_arm_acq_rel]) || [istarget bfin*-*linux*] || [istarget hppa*-*linux*] || [istarget s390*-*-*] @@ -5758,6 +5779,8 @@ proc check_effective_target_sync_char_short { } { || [istarget i?86-*-*] || [istarget x86_64-*-*] || [istarget alpha*-*-*] || [istarget arm*-*-linux-*] + || ([istarget arm*-*-*] + && [check_effective_target_arm_acq_rel]) || [istarget hppa*-*linux*] || [istarget s390*-*-*] || [istarget powerpc*-*-*] |