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| author | John David Anglin <danglin@gcc.gnu.org> | 2019-05-24 23:12:16 +0000 |
|---|---|---|
| committer | John David Anglin <danglin@gcc.gnu.org> | 2019-05-24 23:12:16 +0000 |
| commit | 0241901b0cd82e9d0ba06fa050dad3f051711eb4 (patch) | |
| tree | 6739bb16d4dda32e1d6040649e91baa67f30a876 | |
| parent | 6c7ae8c56f9341f180e097d5eb7ba05cb8eec413 (diff) | |
| download | gcc-0241901b0cd82e9d0ba06fa050dad3f051711eb4.zip gcc-0241901b0cd82e9d0ba06fa050dad3f051711eb4.tar.gz gcc-0241901b0cd82e9d0ba06fa050dad3f051711eb4.tar.bz2 | |
re PR target/90530 (Invalid SUBREG insn generated by reload)
PR target/90530
* config/pa/pa.c (pa_can_change_mode_class): Accept mode changes from
DImode to SImode in floating-point registers on 64-bit target.
* config/pa/pa.md (umulsidi3): Change nonimmediate_operand to
register_operand in xmpyu patterns.
From-SVN: r271611
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/pa/pa.c | 7 | ||||
| -rw-r--r-- | gcc/config/pa/pa.md | 8 |
3 files changed, 16 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 93ba0f2..19c6095 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-05-24 John David Anglin <danglin@gcc.gnu.org> + + PR target/90530 + * config/pa/pa.c (pa_can_change_mode_class): Accept mode changes from + DImode to SImode in floating-point registers on 64-bit target. + * config/pa/pa.md (umulsidi3): Change nonimmediate_operand to + register_operand in xmpyu patterns. + 2019-05-24 Jakub Jelinek <jakub@redhat.com> * tree-core.h (enum omp_clause_code): Add OMP_CLAUSE__CONDTEMP_. diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c index 6509dc4..aa8e346 100644 --- a/gcc/config/pa/pa.c +++ b/gcc/config/pa/pa.c @@ -10011,10 +10011,11 @@ pa_can_change_mode_class (machine_mode from, machine_mode to, /* There is no way to load QImode or HImode values directly from memory to a FP register. SImode loads to the FP registers are not zero extended. On the 64-bit target, this conflicts with the definition - of LOAD_EXTEND_OP. Thus, we can't allow changing between modes with - different sizes in the floating-point registers. */ + of LOAD_EXTEND_OP. Thus, we reject all mode changes in the FP registers + except for DImode to SImode on the 64-bit target. It is handled by + register renaming in pa_print_operand. */ if (MAYBE_FP_REG_CLASS_P (rclass)) - return false; + return TARGET_64BIT && from == DImode && to == SImode; /* TARGET_HARD_REGNO_MODE_OK places modes with sizes larger than a word in specific sets of registers. Thus, we cannot allow changing diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 1b4a524..8308b37 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -5319,8 +5319,8 @@ (define_insn "umulsidi3" [(set (match_operand:DI 0 "register_operand" "=f") - (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f")) - (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))] + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f")) + (zero_extend:DI (match_operand:SI 2 "register_operand" "f"))))] "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT" "xmpyu %1,%2,%0" [(set_attr "type" "fpmuldbl") @@ -5328,7 +5328,7 @@ (define_insn "" [(set (match_operand:DI 0 "register_operand" "=f") - (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f")) + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f")) (match_operand:DI 2 "uint32_operand" "f")))] "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT" "xmpyu %1,%R2,%0" @@ -5337,7 +5337,7 @@ (define_insn "" [(set (match_operand:DI 0 "register_operand" "=f") - (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f")) + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f")) (match_operand:DI 2 "uint32_operand" "f")))] "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT" "xmpyu %1,%2R,%0" |