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| author | David Edelsohn <dje.gcc@gmail.com> | 2013-10-23 14:32:32 +0000 |
|---|---|---|
| committer | David Edelsohn <dje@gcc.gnu.org> | 2013-10-23 10:32:32 -0400 |
| commit | 021b04102ba25a17a164c47678b12cee235f35e9 (patch) | |
| tree | e34207ec1b76d54d55ebb30f2677d53850d9a344 | |
| parent | b1149e84d407a2ce4622a113b5d408475fc9e7a7 (diff) | |
| download | gcc-021b04102ba25a17a164c47678b12cee235f35e9.zip gcc-021b04102ba25a17a164c47678b12cee235f35e9.tar.gz gcc-021b04102ba25a17a164c47678b12cee235f35e9.tar.bz2 | |
re PR target/58838 (mullw sets condition code incorrectly.)
PR target/58838
* config/rs6000/rs6000.md (mulsi3_internal1 and splitter): Add
TARGET_32BIT final condition.
(mulsi3_internal2 and splitter): Same.
From-SVN: r203977
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 8 |
2 files changed, 11 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index acd6620..cf5fef2 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2013-10-23 David Edelsohn <dje.gcc@gmail.com> + + PR target/58838 + * config/rs6000/rs6000.md (mulsi3_internal1 and splitter): Add + TARGET_32BIT final condition. + (mulsi3_internal2 and splitter): Same. + 2013-10-23 Jeff Law <law@redhat.com> * tree-ssa-threadedge.c (thread_across_edge): Do not allow threading diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 567961a..9a0472d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -2699,7 +2699,7 @@ (match_operand:SI 2 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "" + "TARGET_32BIT" "@ mullw. %3,%1,%2 #" @@ -2712,7 +2712,7 @@ (match_operand:SI 2 "gpc_reg_operand" "")) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 3) (mult:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) @@ -2727,7 +2727,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (mult:SI (match_dup 1) (match_dup 2)))] - "" + "TARGET_32BIT" "@ mullw. %0,%1,%2 #" @@ -2741,7 +2741,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (mult:SI (match_dup 1) (match_dup 2)))] - "reload_completed" + "TARGET_32BIT && reload_completed" [(set (match_dup 0) (mult:SI (match_dup 1) (match_dup 2))) (set (match_dup 3) |