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| author | Jim Wilson <wilson@gcc.gnu.org> | 1995-12-18 18:14:50 -0800 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1995-12-18 18:14:50 -0800 |
| commit | 01d7472931b081970fa6ca94d93b313306cf896d (patch) | |
| tree | 4b9d22a4228e15b83edb92101a047d9adccce6f6 | |
| parent | 2973b444e6d50f4e8e7d010904ab23f5e4f80d40 (diff) | |
| download | gcc-01d7472931b081970fa6ca94d93b313306cf896d.zip gcc-01d7472931b081970fa6ca94d93b313306cf896d.tar.gz gcc-01d7472931b081970fa6ca94d93b313306cf896d.tar.bz2 | |
(INITIALIZE_TRAMPOLINE): Likewise for cacheflush.
From-SVN: r10812
| -rw-r--r-- | gcc/config/mips/mips.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 83b10a2..a6a469f 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -2162,12 +2162,11 @@ typedef struct mips_args { } \ \ /* Flush the instruction cache. */ \ - /* ??? Are the modes right? Maybe they should depend on -mint64/-mlong64? */\ /* ??? Should check the return value for errors. */ \ emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "cacheflush"), \ 0, VOIDmode, 3, addr, Pmode, \ - GEN_INT (TRAMPOLINE_SIZE), SImode, \ - GEN_INT (1), SImode); \ + GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\ + GEN_INT (1), TYPE_MODE (integer_type_node)); \ } /* Addressing modes, and classification of registers for them. */ |