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| author | Alex Coplan <alex.coplan@arm.com> | 2020-10-02 11:16:31 +0100 |
|---|---|---|
| committer | Alex Coplan <alex.coplan@arm.com> | 2020-10-02 11:17:00 +0100 |
| commit | 01c288035aa960631dd0ffd9131ed0a824a95f30 (patch) | |
| tree | 55f50f82032d5b5355dd993c95d33a7e6f5452c4 | |
| parent | f8dcbea5d2fb17dca3a7de97f15fc49997222365 (diff) | |
| download | gcc-01c288035aa960631dd0ffd9131ed0a824a95f30.zip gcc-01c288035aa960631dd0ffd9131ed0a824a95f30.tar.gz gcc-01c288035aa960631dd0ffd9131ed0a824a95f30.tar.bz2 | |
aarch64: ilp32 testsuite fixes
This fixes test failures on ilp32 introduced in
r11-3032-gd4febc75e8dfab23bd3132d5747eded918f85107.
The assembler checks in extend-syntax.c simply needed adjusting for
32-bit pointers.
It appears the subsp.c test has never passed on ILP32 due to a missed
optimisation there. Since this isn't a code quality regression, disable
that check on ILP32.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/extend-syntax.c: Fix assembler checks for
ilp32, disable check-function-bodies on ilp32.
* gcc.target/aarch64/subsp.c: Only check second scan-assembler
on lp64 since the code on ilp32 is missing the optimization
needed for this test to pass.
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/extend-syntax.c | 13 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/aarch64/subsp.c | 2 |
2 files changed, 12 insertions, 3 deletions
diff --git a/gcc/testsuite/gcc.target/aarch64/extend-syntax.c b/gcc/testsuite/gcc.target/aarch64/extend-syntax.c index 23fa9f4..1bfcdb5 100644 --- a/gcc/testsuite/gcc.target/aarch64/extend-syntax.c +++ b/gcc/testsuite/gcc.target/aarch64/extend-syntax.c @@ -20,6 +20,7 @@ unsigned long long *add1(unsigned long long *p, unsigned x) */ unsigned long long add2(unsigned long long x, unsigned y) { + /* { dg-final { scan-assembler-times "add\tx0, x0, w1, uxtw" 1 { target ilp32 } } } */ return x + y; } @@ -34,6 +35,9 @@ double *add3(double *p, int x) return p + x; } +// add1 and add3 should both generate this on ILP32: +/* { dg-final { scan-assembler-times "add\tw0, w0, w1, lsl 3" 2 { target ilp32 } } } */ + // Hits *sub_zero_extendsi_di (*sub_<optab><ALLX:mode>_<GPI:mode>). /* ** sub1: @@ -42,6 +46,7 @@ double *add3(double *p, int x) */ unsigned long long sub1(unsigned long long x, unsigned n) { + /* { dg-final { scan-assembler-times "sub\tx0, x0, w1, uxtw" 1 { target ilp32 } } } */ return x - n; } @@ -67,6 +72,9 @@ double *sub3(double *p, int n) return p - n; } +// sub2 and sub3 should both generate this on ILP32: +/* { dg-final { scan-assembler-times "sub\tw0, w0, w1, lsl 3" 2 { target ilp32 } } } */ + // Hits *adds_zero_extendsi_di (*adds_<optab><ALLX:mode>_<GPI:mode>). int adds1(unsigned long long x, unsigned y) { @@ -97,7 +105,8 @@ int subs1(unsigned long long x, unsigned y) unsigned long long *w; int subs2(unsigned long long *x, int y) { - /* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 } } */ + /* { dg-final { scan-assembler-times "subs\tx\[0-9\]+, x\[0-9\]+, w\[0-9\]+, sxtw 3" 1 { target lp64 } } } */ + /* { dg-final { scan-assembler-times "subs\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" 1 { target ilp32 } } } */ unsigned long long *t = x - y; w = t; return !!t; @@ -117,4 +126,4 @@ int cmp2(unsigned long long x, int y) return x == ((unsigned long long)y << 3); } -/* { dg-final { check-function-bodies "**" "" "" } } */ +/* { dg-final { check-function-bodies "**" "" "" { target lp64 } } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/subsp.c b/gcc/testsuite/gcc.target/aarch64/subsp.c index 341b83d..e7f61e0 100644 --- a/gcc/testsuite/gcc.target/aarch64/subsp.c +++ b/gcc/testsuite/gcc.target/aarch64/subsp.c @@ -16,4 +16,4 @@ f2 (int *x, int y) } /* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*\n" } } */ -/* { dg-final { scan-assembler "sub\tsp, sp, w\[0-9\]*, sxtw 4\n" } } */ +/* { dg-final { scan-assembler "sub\tsp, sp, w\[0-9\]*, sxtw 4\n" { target lp64 } } } */ |