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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-12-16 13:14:46 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-12-16 13:14:46 +0000 |
| commit | ed2def05fefdf59e42ad6f13262e5323030e1610 (patch) | |
| tree | 09edc8080838f8853d9e7cbeb41973402f229efa | |
| parent | c67b6f268397b2fc20e72da19e276d2b027ddee4 (diff) | |
| download | gcc-ed2def05fefdf59e42ad6f13262e5323030e1610.zip gcc-ed2def05fefdf59e42ad6f13262e5323030e1610.tar.gz gcc-ed2def05fefdf59e42ad6f13262e5323030e1610.tar.bz2 | |
The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2 doesn't support RSC with an immediate.
The negdi2 patterns for ARM and Thumb-2 are duplicated because Thumb-2
doesn't support RSC with an immediate. We can however emulate RSC with
zero using a shifted SBC. If we add this to subsi3_carryin the negdi
patterns can be merged, simplifying things a bit. This should generate
identical code in all cases.
gcc/
* config/arm/arm.md (subsi3_carryin): Add Thumb-2 RSC #0.
(arm_negdi2) Rename to negdi2_insn, allow on Thumb-2.
* config/arm/thumb2.md (thumb2_negdi2): Remove pattern.
From-SVN: r243745
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 22 | ||||
| -rw-r--r-- | gcc/config/arm/thumb2.md | 26 |
3 files changed, 18 insertions, 36 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index daa0458..bdbadd3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2016-12-16 Wilco Dijkstra <wdijkstr@arm.com> + * config/arm/arm.md (subsi3_carryin): Add Thumb-2 RSC #0. + (arm_negdi2) Rename to negdi2_insn, allow on Thumb-2. + * config/arm/thumb2.md (thumb2_negdi2): Remove pattern. + +2016-12-16 Wilco Dijkstra <wdijkstr@arm.com> + * config/arm/arm.c (thumb_core_reg_alloc_order): Swap R12 and R14. 2016-12-16 Claudiu Zissulescu <claziss@synopsys.com> diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index d561a4b..ff1f565 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1129,19 +1129,20 @@ ) (define_insn "*subsi3_carryin" - [(set (match_operand:SI 0 "s_register_operand" "=r,r") - (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I") - (match_operand:SI 2 "s_register_operand" "r,r")) - (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + [(set (match_operand:SI 0 "s_register_operand" "=r,r,r") + (minus:SI (minus:SI (match_operand:SI 1 "reg_or_int_operand" "r,I,Pz") + (match_operand:SI 2 "s_register_operand" "r,r,r")) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] "TARGET_32BIT" "@ sbc%?\\t%0, %1, %2 - rsc%?\\t%0, %2, %1" + rsc%?\\t%0, %2, %1 + sbc%?\\t%0, %2, %2, lsl #1" [(set_attr "conds" "use") - (set_attr "arch" "*,a") + (set_attr "arch" "*,a,t2") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "adc_reg,adc_imm")] + (set_attr "type" "adc_reg,adc_imm,alu_shift_imm")] ) (define_insn "*subsi3_carryin_const" @@ -4681,12 +4682,13 @@ ;; The constraints here are to prevent a *partial* overlap (where %Q0 == %R1). ;; The first alternative allows the common case of a *full* overlap. -(define_insn_and_split "*arm_negdi2" +(define_insn_and_split "*negdi2_insn" [(set (match_operand:DI 0 "s_register_operand" "=r,&r") (neg:DI (match_operand:DI 1 "s_register_operand" "0,r"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" - "#" ; "rsbs\\t%Q0, %Q1, #0\;rsc\\t%R0, %R1, #0" + "TARGET_32BIT" + "#" ; rsbs %Q0, %Q1, #0; rsc %R0, %R1, #0 (ARM) + ; negs %Q0, %Q1 ; sbc %R0, %R1, %R1, lsl #1 (Thumb-2) "&& reload_completed" [(parallel [(set (reg:CC CC_REGNUM) (compare:CC (const_int 0) (match_dup 1))) diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 9b078a5..e8fff07 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -125,32 +125,6 @@ (set_attr "type" "multiple")] ) -;; Thumb-2 does not have rsc, so use a clever trick with shifter operands. -(define_insn_and_split "*thumb2_negdi2" - [(set (match_operand:DI 0 "s_register_operand" "=&r,r") - (neg:DI (match_operand:DI 1 "s_register_operand" "?r,0"))) - (clobber (reg:CC CC_REGNUM))] - "TARGET_THUMB2" - "#" ; negs\\t%Q0, %Q1\;sbc\\t%R0, %R1, %R1, lsl #1 - "&& reload_completed" - [(parallel [(set (reg:CC CC_REGNUM) - (compare:CC (const_int 0) (match_dup 1))) - (set (match_dup 0) (minus:SI (const_int 0) (match_dup 1)))]) - (set (match_dup 2) (minus:SI (minus:SI (match_dup 3) - (ashift:SI (match_dup 3) - (const_int 1))) - (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] - { - operands[2] = gen_highpart (SImode, operands[0]); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[3] = gen_highpart (SImode, operands[1]); - operands[1] = gen_lowpart (SImode, operands[1]); - } - [(set_attr "conds" "clob") - (set_attr "length" "8") - (set_attr "type" "multiple")] -) - (define_insn_and_split "*thumb2_abssi2" [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r") (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))) |