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| author | Dennis Zhang <dennis.zhang@arm.com> | 2019-06-28 08:42:09 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2019-06-28 08:42:09 +0000 |
| commit | cd65e2652d2c38eaa63f01ccc3a60bb5225235d2 (patch) | |
| tree | 2946c42737d359f3725667360d353672df17d405 | |
| parent | 494cd9e8050006089381f5361953f5cecb5de861 (diff) | |
| download | gcc-cd65e2652d2c38eaa63f01ccc3a60bb5225235d2.zip gcc-cd65e2652d2c38eaa63f01ccc3a60bb5225235d2.tar.gz gcc-cd65e2652d2c38eaa63f01ccc3a60bb5225235d2.tar.bz2 | |
[Arm] Remove constraint strings from define_expand constructs in the back end
A number of Arm define_expand patterns have specified constraints for
their operands. But the constraint strings are ignored at expand time
and are therefore redundant/useless. We now avoid specifying constraints
in new define_expands, but we should clean up the existing define_expand
definitions.
2019-06-28 Dennis Zhang <dennis.zhang@arm.com>
* config/arm/arm.md: Remove redundant constraints from
define_expand but leave reload_inm and reload_outm patterns
untouched since they need special constraints to work.
* config/arm/arm-fixed.md: Remove redundant constraints from
define_expand.
* config/arm/iwmmxt.md: Likewise.
* config/arm/neon.md: Likewise.
* config/arm/sync.md: Likewise.
* config/arm/thumb1.md: Likewise.
* config/arm/vec-common.md: Likewise.
From-SVN: r272779
| -rw-r--r-- | gcc/ChangeLog | 13 | ||||
| -rw-r--r-- | gcc/config/arm/arm-fixed.md | 54 | ||||
| -rw-r--r-- | gcc/config/arm/arm.md | 627 | ||||
| -rw-r--r-- | gcc/config/arm/iwmmxt.md | 16 | ||||
| -rw-r--r-- | gcc/config/arm/neon.md | 454 | ||||
| -rw-r--r-- | gcc/config/arm/sync.md | 10 | ||||
| -rw-r--r-- | gcc/config/arm/thumb1.md | 24 | ||||
| -rw-r--r-- | gcc/config/arm/vec-common.md | 54 |
8 files changed, 634 insertions, 618 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f8bd2b2..898b5a1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2019-06-28 Dennis Zhang <dennis.zhang@arm.com> + + * config/arm/arm.md: Remove redundant constraints from + define_expand but leave reload_inm and reload_outm patterns + untouched since they need special constraints to work. + * config/arm/arm-fixed.md: Remove redundant constraints from + define_expand. + * config/arm/iwmmxt.md: Likewise. + * config/arm/neon.md: Likewise. + * config/arm/sync.md: Likewise. + * config/arm/thumb1.md: Likewise. + * config/arm/vec-common.md: Likewise. + 2019-06-27 Ilia Diachkov <ilia.diachkov@optimitech.com> * doc/install.texi: Document --disable-tm-clone-registry. diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index 6534ed4..fcab40d 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -98,9 +98,9 @@ ; Note: none of these do any rounding. (define_expand "mulqq3" - [(set (match_operand:QQ 0 "s_register_operand" "") - (mult:QQ (match_operand:QQ 1 "s_register_operand" "") - (match_operand:QQ 2 "s_register_operand" "")))] + [(set (match_operand:QQ 0 "s_register_operand") + (mult:QQ (match_operand:QQ 1 "s_register_operand") + (match_operand:QQ 2 "s_register_operand")))] "TARGET_DSP_MULTIPLY && arm_arch_thumb2" { rtx tmp1 = gen_reg_rtx (HImode); @@ -116,9 +116,9 @@ }) (define_expand "mulhq3" - [(set (match_operand:HQ 0 "s_register_operand" "") - (mult:HQ (match_operand:HQ 1 "s_register_operand" "") - (match_operand:HQ 2 "s_register_operand" "")))] + [(set (match_operand:HQ 0 "s_register_operand") + (mult:HQ (match_operand:HQ 1 "s_register_operand") + (match_operand:HQ 2 "s_register_operand")))] "TARGET_DSP_MULTIPLY && arm_arch_thumb2" { rtx tmp = gen_reg_rtx (SImode); @@ -134,9 +134,9 @@ }) (define_expand "mulsq3" - [(set (match_operand:SQ 0 "s_register_operand" "") - (mult:SQ (match_operand:SQ 1 "s_register_operand" "") - (match_operand:SQ 2 "s_register_operand" "")))] + [(set (match_operand:SQ 0 "s_register_operand") + (mult:SQ (match_operand:SQ 1 "s_register_operand") + (match_operand:SQ 2 "s_register_operand")))] "TARGET_32BIT" { rtx tmp1 = gen_reg_rtx (DImode); @@ -156,9 +156,9 @@ ;; Accumulator multiplies. (define_expand "mulsa3" - [(set (match_operand:SA 0 "s_register_operand" "") - (mult:SA (match_operand:SA 1 "s_register_operand" "") - (match_operand:SA 2 "s_register_operand" "")))] + [(set (match_operand:SA 0 "s_register_operand") + (mult:SA (match_operand:SA 1 "s_register_operand") + (match_operand:SA 2 "s_register_operand")))] "TARGET_32BIT" { rtx tmp1 = gen_reg_rtx (DImode); @@ -175,9 +175,9 @@ }) (define_expand "mulusa3" - [(set (match_operand:USA 0 "s_register_operand" "") - (mult:USA (match_operand:USA 1 "s_register_operand" "") - (match_operand:USA 2 "s_register_operand" "")))] + [(set (match_operand:USA 0 "s_register_operand") + (mult:USA (match_operand:USA 1 "s_register_operand") + (match_operand:USA 2 "s_register_operand")))] "TARGET_32BIT" { rtx tmp1 = gen_reg_rtx (DImode); @@ -317,9 +317,9 @@ (const_int 32)))]) (define_expand "mulha3" - [(set (match_operand:HA 0 "s_register_operand" "") - (mult:HA (match_operand:HA 1 "s_register_operand" "") - (match_operand:HA 2 "s_register_operand" "")))] + [(set (match_operand:HA 0 "s_register_operand") + (mult:HA (match_operand:HA 1 "s_register_operand") + (match_operand:HA 2 "s_register_operand")))] "TARGET_DSP_MULTIPLY && arm_arch_thumb2" { rtx tmp = gen_reg_rtx (SImode); @@ -333,9 +333,9 @@ }) (define_expand "muluha3" - [(set (match_operand:UHA 0 "s_register_operand" "") - (mult:UHA (match_operand:UHA 1 "s_register_operand" "") - (match_operand:UHA 2 "s_register_operand" "")))] + [(set (match_operand:UHA 0 "s_register_operand") + (mult:UHA (match_operand:UHA 1 "s_register_operand") + (match_operand:UHA 2 "s_register_operand")))] "TARGET_DSP_MULTIPLY" { rtx tmp1 = gen_reg_rtx (SImode); @@ -353,9 +353,9 @@ }) (define_expand "ssmulha3" - [(set (match_operand:HA 0 "s_register_operand" "") - (ss_mult:HA (match_operand:HA 1 "s_register_operand" "") - (match_operand:HA 2 "s_register_operand" "")))] + [(set (match_operand:HA 0 "s_register_operand") + (ss_mult:HA (match_operand:HA 1 "s_register_operand") + (match_operand:HA 2 "s_register_operand")))] "TARGET_32BIT && TARGET_DSP_MULTIPLY && arm_arch6" { rtx tmp = gen_reg_rtx (SImode); @@ -373,9 +373,9 @@ }) (define_expand "usmuluha3" - [(set (match_operand:UHA 0 "s_register_operand" "") - (us_mult:UHA (match_operand:UHA 1 "s_register_operand" "") - (match_operand:UHA 2 "s_register_operand" "")))] + [(set (match_operand:UHA 0 "s_register_operand") + (us_mult:UHA (match_operand:UHA 1 "s_register_operand") + (match_operand:UHA 2 "s_register_operand")))] "TARGET_INT_SIMD" { rtx tmp1 = gen_reg_rtx (SImode); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index a7fa410..8f4a4c2 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -444,9 +444,9 @@ (define_expand "adddi3" [(parallel - [(set (match_operand:DI 0 "s_register_operand" "") - (plus:DI (match_operand:DI 1 "s_register_operand" "") - (match_operand:DI 2 "arm_adddi_operand" ""))) + [(set (match_operand:DI 0 "s_register_operand") + (plus:DI (match_operand:DI 1 "s_register_operand") + (match_operand:DI 2 "arm_adddi_operand"))) (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" " @@ -573,9 +573,9 @@ }) (define_expand "addsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (plus:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "reg_or_int_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (plus:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_EITHER" " if (TARGET_32BIT && CONST_INT_P (operands[2])) @@ -1266,26 +1266,26 @@ ") (define_expand "addsf3" - [(set (match_operand:SF 0 "s_register_operand" "") - (plus:SF (match_operand:SF 1 "s_register_operand" "") - (match_operand:SF 2 "s_register_operand" "")))] + [(set (match_operand:SF 0 "s_register_operand") + (plus:SF (match_operand:SF 1 "s_register_operand") + (match_operand:SF 2 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT" " ") (define_expand "adddf3" - [(set (match_operand:DF 0 "s_register_operand" "") - (plus:DF (match_operand:DF 1 "s_register_operand" "") - (match_operand:DF 2 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (plus:DF (match_operand:DF 1 "s_register_operand") + (match_operand:DF 2 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" " ") (define_expand "subdi3" [(parallel - [(set (match_operand:DI 0 "s_register_operand" "") - (minus:DI (match_operand:DI 1 "s_register_operand" "") - (match_operand:DI 2 "s_register_operand" ""))) + [(set (match_operand:DI 0 "s_register_operand") + (minus:DI (match_operand:DI 1 "s_register_operand") + (match_operand:DI 2 "s_register_operand"))) (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" " @@ -1459,9 +1459,9 @@ ) (define_expand "subsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (minus:SI (match_operand:SI 1 "reg_or_int_operand" "") - (match_operand:SI 2 "s_register_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (minus:SI (match_operand:SI 1 "reg_or_int_operand") + (match_operand:SI 2 "s_register_operand")))] "TARGET_EITHER" " if (CONST_INT_P (operands[1])) @@ -1562,17 +1562,17 @@ ) (define_expand "subsf3" - [(set (match_operand:SF 0 "s_register_operand" "") - (minus:SF (match_operand:SF 1 "s_register_operand" "") - (match_operand:SF 2 "s_register_operand" "")))] + [(set (match_operand:SF 0 "s_register_operand") + (minus:SF (match_operand:SF 1 "s_register_operand") + (match_operand:SF 2 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT" " ") (define_expand "subdf3" - [(set (match_operand:DF 0 "s_register_operand" "") - (minus:DF (match_operand:DF 1 "s_register_operand" "") - (match_operand:DF 2 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (minus:DF (match_operand:DF 1 "s_register_operand") + (match_operand:DF 2 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" " ") @@ -1581,9 +1581,9 @@ ;; Multiplication insns (define_expand "mulhi3" - [(set (match_operand:HI 0 "s_register_operand" "") - (mult:HI (match_operand:HI 1 "s_register_operand" "") - (match_operand:HI 2 "s_register_operand" "")))] + [(set (match_operand:HI 0 "s_register_operand") + (mult:HI (match_operand:HI 1 "s_register_operand") + (match_operand:HI 2 "s_register_operand")))] "TARGET_DSP_MULTIPLY" " { @@ -1595,9 +1595,9 @@ ) (define_expand "mulsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (mult:SI (match_operand:SI 2 "s_register_operand" "") - (match_operand:SI 1 "s_register_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (mult:SI (match_operand:SI 2 "s_register_operand") + (match_operand:SI 1 "s_register_operand")))] "TARGET_EITHER" "" ) @@ -1783,12 +1783,12 @@ ) (define_expand "maddsidi4" - [(set (match_operand:DI 0 "s_register_operand" "") + [(set (match_operand:DI 0 "s_register_operand") (plus:DI (mult:DI - (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")) - (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))) - (match_operand:DI 3 "s_register_operand" "")))] + (sign_extend:DI (match_operand:SI 1 "s_register_operand")) + (sign_extend:DI (match_operand:SI 2 "s_register_operand"))) + (match_operand:DI 3 "s_register_operand")))] "TARGET_32BIT" "") @@ -1825,10 +1825,10 @@ ;; expander and two different starred insns. (define_expand "mulsidi3" - [(set (match_operand:DI 0 "s_register_operand" "") + [(set (match_operand:DI 0 "s_register_operand") (mult:DI - (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")) - (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))))] + (sign_extend:DI (match_operand:SI 1 "s_register_operand")) + (sign_extend:DI (match_operand:SI 2 "s_register_operand"))))] "TARGET_32BIT" "" ) @@ -1856,10 +1856,10 @@ ) (define_expand "umulsidi3" - [(set (match_operand:DI 0 "s_register_operand" "") + [(set (match_operand:DI 0 "s_register_operand") (mult:DI - (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")) - (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))))] + (zero_extend:DI (match_operand:SI 1 "s_register_operand")) + (zero_extend:DI (match_operand:SI 2 "s_register_operand"))))] "TARGET_32BIT" "" ) @@ -1887,12 +1887,12 @@ ) (define_expand "umaddsidi4" - [(set (match_operand:DI 0 "s_register_operand" "") + [(set (match_operand:DI 0 "s_register_operand") (plus:DI (mult:DI - (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")) - (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))) - (match_operand:DI 3 "s_register_operand" "")))] + (zero_extend:DI (match_operand:SI 1 "s_register_operand")) + (zero_extend:DI (match_operand:SI 2 "s_register_operand"))) + (match_operand:DI 3 "s_register_operand")))] "TARGET_32BIT" "") @@ -1924,12 +1924,12 @@ (define_expand "smulsi3_highpart" [(parallel - [(set (match_operand:SI 0 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand") (truncate:SI (lshiftrt:DI (mult:DI - (sign_extend:DI (match_operand:SI 1 "s_register_operand" "")) - (sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))) + (sign_extend:DI (match_operand:SI 1 "s_register_operand")) + (sign_extend:DI (match_operand:SI 2 "s_register_operand"))) (const_int 32)))) (clobber (match_scratch:SI 3 ""))])] "TARGET_32BIT" @@ -1968,12 +1968,12 @@ (define_expand "umulsi3_highpart" [(parallel - [(set (match_operand:SI 0 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand") (truncate:SI (lshiftrt:DI (mult:DI - (zero_extend:DI (match_operand:SI 1 "s_register_operand" "")) - (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))) + (zero_extend:DI (match_operand:SI 1 "s_register_operand")) + (zero_extend:DI (match_operand:SI 2 "s_register_operand"))) (const_int 32)))) (clobber (match_scratch:SI 3 ""))])] "TARGET_32BIT" @@ -2152,17 +2152,17 @@ (set_attr "predicable" "yes")]) (define_expand "mulsf3" - [(set (match_operand:SF 0 "s_register_operand" "") - (mult:SF (match_operand:SF 1 "s_register_operand" "") - (match_operand:SF 2 "s_register_operand" "")))] + [(set (match_operand:SF 0 "s_register_operand") + (mult:SF (match_operand:SF 1 "s_register_operand") + (match_operand:SF 2 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT" " ") (define_expand "muldf3" - [(set (match_operand:DF 0 "s_register_operand" "") - (mult:DF (match_operand:DF 1 "s_register_operand" "") - (match_operand:DF 2 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (mult:DF (match_operand:DF 1 "s_register_operand") + (match_operand:DF 2 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" " ") @@ -2170,16 +2170,16 @@ ;; Division insns (define_expand "divsf3" - [(set (match_operand:SF 0 "s_register_operand" "") - (div:SF (match_operand:SF 1 "s_register_operand" "") - (match_operand:SF 2 "s_register_operand" "")))] + [(set (match_operand:SF 0 "s_register_operand") + (div:SF (match_operand:SF 1 "s_register_operand") + (match_operand:SF 2 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT" "") (define_expand "divdf3" - [(set (match_operand:DF 0 "s_register_operand" "") - (div:DF (match_operand:DF 1 "s_register_operand" "") - (match_operand:DF 2 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (div:DF (match_operand:DF 1 "s_register_operand") + (match_operand:DF 2 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "") @@ -2270,9 +2270,9 @@ ) (define_expand "anddi3" - [(set (match_operand:DI 0 "s_register_operand" "") - (and:DI (match_operand:DI 1 "s_register_operand" "") - (match_operand:DI 2 "neon_inv_logic_op2" "")))] + [(set (match_operand:DI 0 "s_register_operand") + (and:DI (match_operand:DI 1 "s_register_operand") + (match_operand:DI 2 "neon_inv_logic_op2")))] "TARGET_32BIT" " if (!TARGET_NEON && !TARGET_IWMMXT) @@ -2374,9 +2374,9 @@ ) (define_expand "andsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (and:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "reg_or_int_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (and:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_EITHER" " if (TARGET_32BIT) @@ -2727,10 +2727,10 @@ ;;; this insv pattern, so this pattern needs to be reevalutated. (define_expand "insv" - [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") - (match_operand 1 "general_operand" "") - (match_operand 2 "general_operand" "")) - (match_operand 3 "reg_or_int_operand" ""))] + [(set (zero_extract (match_operand 0 "nonimmediate_operand") + (match_operand 1 "general_operand") + (match_operand 2 "general_operand")) + (match_operand 3 "reg_or_int_operand"))] "TARGET_ARM || arm_arch_thumb2" " { @@ -3151,9 +3151,9 @@ ) (define_expand "iordi3" - [(set (match_operand:DI 0 "s_register_operand" "") - (ior:DI (match_operand:DI 1 "s_register_operand" "") - (match_operand:DI 2 "neon_logic_op2" "")))] + [(set (match_operand:DI 0 "s_register_operand") + (ior:DI (match_operand:DI 1 "s_register_operand") + (match_operand:DI 2 "neon_logic_op2")))] "TARGET_32BIT" " if (!TARGET_NEON && !TARGET_IWMMXT) @@ -3246,9 +3246,9 @@ ) (define_expand "iorsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (ior:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "reg_or_int_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (ior:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_EITHER" " if (CONST_INT_P (operands[2])) @@ -3348,9 +3348,9 @@ ) (define_expand "xordi3" - [(set (match_operand:DI 0 "s_register_operand" "") - (xor:DI (match_operand:DI 1 "s_register_operand" "") - (match_operand:DI 2 "arm_xordi_operand" "")))] + [(set (match_operand:DI 0 "s_register_operand") + (xor:DI (match_operand:DI 1 "s_register_operand") + (match_operand:DI 2 "arm_xordi_operand")))] "TARGET_32BIT" { /* The iWMMXt pattern for xordi3 accepts only register operands but we want @@ -3445,9 +3445,9 @@ ) (define_expand "xorsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (xor:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "reg_or_int_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (xor:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_EITHER" "if (CONST_INT_P (operands[2])) { @@ -3686,9 +3686,9 @@ (define_expand "smaxsi3" [(parallel [ - (set (match_operand:SI 0 "s_register_operand" "") - (smax:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" ""))) + (set (match_operand:SI 0 "s_register_operand") + (smax:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_rhs_operand"))) (clobber (reg:CC CC_REGNUM))])] "TARGET_32BIT" " @@ -3746,9 +3746,9 @@ (define_expand "sminsi3" [(parallel [ - (set (match_operand:SI 0 "s_register_operand" "") - (smin:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" ""))) + (set (match_operand:SI 0 "s_register_operand") + (smin:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_rhs_operand"))) (clobber (reg:CC CC_REGNUM))])] "TARGET_32BIT" " @@ -3796,9 +3796,9 @@ (define_expand "umaxsi3" [(parallel [ - (set (match_operand:SI 0 "s_register_operand" "") - (umax:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" ""))) + (set (match_operand:SI 0 "s_register_operand") + (umax:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_rhs_operand"))) (clobber (reg:CC CC_REGNUM))])] "TARGET_32BIT" "" @@ -3829,9 +3829,9 @@ (define_expand "uminsi3" [(parallel [ - (set (match_operand:SI 0 "s_register_operand" "") - (umin:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" ""))) + (set (match_operand:SI 0 "s_register_operand") + (umin:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_rhs_operand"))) (clobber (reg:CC CC_REGNUM))])] "TARGET_32BIT" "" @@ -4037,9 +4037,9 @@ ;; Shift and rotation insns (define_expand "ashldi3" - [(set (match_operand:DI 0 "s_register_operand" "") - (ashift:DI (match_operand:DI 1 "s_register_operand" "") - (match_operand:SI 2 "general_operand" "")))] + [(set (match_operand:DI 0 "s_register_operand") + (ashift:DI (match_operand:DI 1 "s_register_operand") + (match_operand:SI 2 "general_operand")))] "TARGET_32BIT" " if (TARGET_NEON) @@ -4079,9 +4079,9 @@ ) (define_expand "ashlsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (ashift:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (ashift:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_rhs_operand")))] "TARGET_EITHER" " if (CONST_INT_P (operands[2]) @@ -4094,9 +4094,9 @@ ) (define_expand "ashrdi3" - [(set (match_operand:DI 0 "s_register_operand" "") - (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "") - (match_operand:SI 2 "reg_or_int_operand" "")))] + [(set (match_operand:DI 0 "s_register_operand") + (ashiftrt:DI (match_operand:DI 1 "s_register_operand") + (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " if (TARGET_NEON) @@ -4130,9 +4130,9 @@ ) (define_expand "ashrsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (ashiftrt:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_rhs_operand")))] "TARGET_EITHER" " if (CONST_INT_P (operands[2]) @@ -4142,9 +4142,9 @@ ) (define_expand "lshrdi3" - [(set (match_operand:DI 0 "s_register_operand" "") - (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "") - (match_operand:SI 2 "reg_or_int_operand" "")))] + [(set (match_operand:DI 0 "s_register_operand") + (lshiftrt:DI (match_operand:DI 1 "s_register_operand") + (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " if (TARGET_NEON) @@ -4178,9 +4178,9 @@ ) (define_expand "lshrsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (lshiftrt:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (lshiftrt:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_rhs_operand")))] "TARGET_EITHER" " if (CONST_INT_P (operands[2]) @@ -4193,9 +4193,9 @@ ) (define_expand "rotlsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (rotatert:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "reg_or_int_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (rotatert:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "reg_or_int_operand")))] "TARGET_32BIT" " if (CONST_INT_P (operands[2])) @@ -4210,9 +4210,9 @@ ) (define_expand "rotrsi3" - [(set (match_operand:SI 0 "s_register_operand" "") - (rotatert:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "arm_rhs_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (rotatert:SI (match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "arm_rhs_operand")))] "TARGET_EITHER" " if (TARGET_32BIT) @@ -4320,10 +4320,10 @@ ;; to reduce register pressure later on. (define_expand "extzv" - [(set (match_operand 0 "s_register_operand" "") - (zero_extract (match_operand 1 "nonimmediate_operand" "") - (match_operand 2 "const_int_operand" "") - (match_operand 3 "const_int_operand" "")))] + [(set (match_operand 0 "s_register_operand") + (zero_extract (match_operand 1 "nonimmediate_operand") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] "TARGET_THUMB1 || arm_arch_thumb2" " { @@ -4401,20 +4401,20 @@ ;; Helper for extzv, for the Thumb-1 register-shifts case. (define_expand "extzv_t1" - [(set (match_operand:SI 4 "s_register_operand" "") - (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "") - (match_operand:SI 2 "const_int_operand" ""))) - (set (match_operand:SI 0 "s_register_operand" "") + [(set (match_operand:SI 4 "s_register_operand") + (ashift:SI (match_operand:SI 1 "nonimmediate_operand") + (match_operand:SI 2 "const_int_operand"))) + (set (match_operand:SI 0 "s_register_operand") (lshiftrt:SI (match_dup 4) - (match_operand:SI 3 "const_int_operand" "")))] + (match_operand:SI 3 "const_int_operand")))] "TARGET_THUMB1" "") (define_expand "extv" - [(set (match_operand 0 "s_register_operand" "") - (sign_extract (match_operand 1 "nonimmediate_operand" "") - (match_operand 2 "const_int_operand" "") - (match_operand 3 "const_int_operand" "")))] + [(set (match_operand 0 "s_register_operand") + (sign_extract (match_operand 1 "nonimmediate_operand") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] "arm_arch_thumb2" { HOST_WIDE_INT width = INTVAL (operands[2]); @@ -4472,10 +4472,10 @@ ; Helper to expand register forms of extv with the proper modes. (define_expand "extv_regsi" - [(set (match_operand:SI 0 "s_register_operand" "") - (sign_extract:SI (match_operand:SI 1 "s_register_operand" "") - (match_operand 2 "const_int_operand" "") - (match_operand 3 "const_int_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (sign_extract:SI (match_operand:SI 1 "s_register_operand") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] "" { }) @@ -4676,8 +4676,8 @@ (define_expand "negdi2" [(parallel - [(set (match_operand:DI 0 "s_register_operand" "") - (neg:DI (match_operand:DI 1 "s_register_operand" ""))) + [(set (match_operand:DI 0 "s_register_operand") + (neg:DI (match_operand:DI 1 "s_register_operand"))) (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" { @@ -4730,8 +4730,8 @@ ) (define_expand "negsi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (neg:SI (match_operand:SI 1 "s_register_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (neg:SI (match_operand:SI 1 "s_register_operand")))] "TARGET_EITHER" "" ) @@ -4749,15 +4749,15 @@ ) (define_expand "negsf2" - [(set (match_operand:SF 0 "s_register_operand" "") - (neg:SF (match_operand:SF 1 "s_register_operand" "")))] + [(set (match_operand:SF 0 "s_register_operand") + (neg:SF (match_operand:SF 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT" "" ) (define_expand "negdf2" - [(set (match_operand:DF 0 "s_register_operand" "") - (neg:DF (match_operand:DF 1 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (neg:DF (match_operand:DF 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "") @@ -4881,8 +4881,8 @@ (define_expand "abssi2" [(parallel - [(set (match_operand:SI 0 "s_register_operand" "") - (abs:SI (match_operand:SI 1 "s_register_operand" ""))) + [(set (match_operand:SI 0 "s_register_operand") + (abs:SI (match_operand:SI 1 "s_register_operand"))) (clobber (match_dup 2))])] "TARGET_EITHER" " @@ -5010,32 +5010,32 @@ ) (define_expand "abssf2" - [(set (match_operand:SF 0 "s_register_operand" "") - (abs:SF (match_operand:SF 1 "s_register_operand" "")))] + [(set (match_operand:SF 0 "s_register_operand") + (abs:SF (match_operand:SF 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT" "") (define_expand "absdf2" - [(set (match_operand:DF 0 "s_register_operand" "") - (abs:DF (match_operand:DF 1 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (abs:DF (match_operand:DF 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" "") (define_expand "sqrtsf2" - [(set (match_operand:SF 0 "s_register_operand" "") - (sqrt:SF (match_operand:SF 1 "s_register_operand" "")))] + [(set (match_operand:SF 0 "s_register_operand") + (sqrt:SF (match_operand:SF 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT" "") (define_expand "sqrtdf2" - [(set (match_operand:DF 0 "s_register_operand" "") - (sqrt:DF (match_operand:DF 1 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (sqrt:DF (match_operand:DF 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" "") (define_expand "one_cmpldi2" - [(set (match_operand:DI 0 "s_register_operand" "") - (not:DI (match_operand:DI 1 "s_register_operand" "")))] + [(set (match_operand:DI 0 "s_register_operand") + (not:DI (match_operand:DI 1 "s_register_operand")))] "TARGET_32BIT" " if (!TARGET_NEON && !TARGET_IWMMXT) @@ -5084,8 +5084,8 @@ ) (define_expand "one_cmplsi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (not:SI (match_operand:SI 1 "s_register_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (not:SI (match_operand:SI 1 "s_register_operand")))] "TARGET_EITHER" "" ) @@ -5128,8 +5128,8 @@ ;; Fixed <--> Floating conversion insns (define_expand "floatsihf2" - [(set (match_operand:HF 0 "general_operand" "") - (float:HF (match_operand:SI 1 "general_operand" "")))] + [(set (match_operand:HF 0 "general_operand") + (float:HF (match_operand:SI 1 "general_operand")))] "TARGET_EITHER" " { @@ -5142,8 +5142,8 @@ ) (define_expand "floatdihf2" - [(set (match_operand:HF 0 "general_operand" "") - (float:HF (match_operand:DI 1 "general_operand" "")))] + [(set (match_operand:HF 0 "general_operand") + (float:HF (match_operand:DI 1 "general_operand")))] "TARGET_EITHER" " { @@ -5156,22 +5156,22 @@ ) (define_expand "floatsisf2" - [(set (match_operand:SF 0 "s_register_operand" "") - (float:SF (match_operand:SI 1 "s_register_operand" "")))] + [(set (match_operand:SF 0 "s_register_operand") + (float:SF (match_operand:SI 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT" " ") (define_expand "floatsidf2" - [(set (match_operand:DF 0 "s_register_operand" "") - (float:DF (match_operand:SI 1 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (float:DF (match_operand:SI 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" " ") (define_expand "fix_trunchfsi2" - [(set (match_operand:SI 0 "general_operand" "") - (fix:SI (fix:HF (match_operand:HF 1 "general_operand" ""))))] + [(set (match_operand:SI 0 "general_operand") + (fix:SI (fix:HF (match_operand:HF 1 "general_operand"))))] "TARGET_EITHER" " { @@ -5182,8 +5182,8 @@ ) (define_expand "fix_trunchfdi2" - [(set (match_operand:DI 0 "general_operand" "") - (fix:DI (fix:HF (match_operand:HF 1 "general_operand" ""))))] + [(set (match_operand:DI 0 "general_operand") + (fix:DI (fix:HF (match_operand:HF 1 "general_operand"))))] "TARGET_EITHER" " { @@ -5194,15 +5194,15 @@ ) (define_expand "fix_truncsfsi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] + [(set (match_operand:SI 0 "s_register_operand") + (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand"))))] "TARGET_32BIT && TARGET_HARD_FLOAT" " ") (define_expand "fix_truncdfsi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] + [(set (match_operand:SI 0 "s_register_operand") + (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand"))))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" " ") @@ -5210,9 +5210,9 @@ ;; Truncation insns (define_expand "truncdfsf2" - [(set (match_operand:SF 0 "s_register_operand" "") + [(set (match_operand:SF 0 "s_register_operand") (float_truncate:SF - (match_operand:DF 1 "s_register_operand" "")))] + (match_operand:DF 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" "" ) @@ -5225,9 +5225,9 @@ ;; a single-step instruction. (define_expand "truncdfhf2" - [(set (match_operand:HF 0 "s_register_operand" "") + [(set (match_operand:HF 0 "s_register_operand") (float_truncate:HF - (match_operand:DF 1 "s_register_operand" "")))] + (match_operand:DF 1 "s_register_operand")))] "(TARGET_EITHER && flag_unsafe_math_optimizations) || (TARGET_32BIT && TARGET_FP16_TO_DOUBLE)" { @@ -5330,8 +5330,8 @@ }) (define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))] "TARGET_EITHER" { if (TARGET_ARM && !arm_arch4 && MEM_P (operands[1])) @@ -5392,8 +5392,8 @@ ) (define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))] "TARGET_EITHER" { if (TARGET_ARM && !arm_arch6 && !MEM_P (operands[1])) @@ -5514,8 +5514,8 @@ ) (define_expand "extendhisi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))] "TARGET_EITHER" { if (TARGET_THUMB1) @@ -5633,9 +5633,9 @@ (define_expand "extendqihi2" [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "") + (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op") (const_int 24))) - (set (match_operand:HI 0 "s_register_operand" "") + (set (match_operand:HI 0 "s_register_operand") (ashiftrt:SI (match_dup 2) (const_int 24)))] "TARGET_ARM" @@ -5665,8 +5665,8 @@ ) (define_expand "extendqisi2" - [(set (match_operand:SI 0 "s_register_operand" "") - (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op")))] "TARGET_EITHER" { if (!arm_arch4 && MEM_P (operands[1])) @@ -5727,8 +5727,8 @@ ) (define_expand "extendsfdf2" - [(set (match_operand:DF 0 "s_register_operand" "") - (float_extend:DF (match_operand:SF 1 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (float_extend:DF (match_operand:SF 1 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" "" ) @@ -5739,8 +5739,8 @@ ;; This is always safe for an extend. (define_expand "extendhfdf2" - [(set (match_operand:DF 0 "s_register_operand" "") - (float_extend:DF (match_operand:HF 1 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (float_extend:DF (match_operand:HF 1 "s_register_operand")))] "TARGET_EITHER" { /* We don't have a direct instruction for this, so go via SFmode. */ @@ -5763,18 +5763,18 @@ ;; I don't think these are a good idea on the arm, there just aren't enough ;; registers ;;(define_expand "loadti" -;; [(set (match_operand:TI 0 "s_register_operand" "") -;; (mem:TI (match_operand:SI 1 "address_operand" "")))] +;; [(set (match_operand:TI 0 "s_register_operand") +;; (mem:TI (match_operand:SI 1 "address_operand")))] ;; "" "") ;;(define_expand "storeti" -;; [(set (mem:TI (match_operand:TI 0 "address_operand" "")) -;; (match_operand:TI 1 "s_register_operand" ""))] +;; [(set (mem:TI (match_operand:TI 0 "address_operand")) +;; (match_operand:TI 1 "s_register_operand"))] ;; "" "") ;;(define_expand "movti" -;; [(set (match_operand:TI 0 "general_operand" "") -;; (match_operand:TI 1 "general_operand" ""))] +;; [(set (match_operand:TI 0 "general_operand") +;; (match_operand:TI 1 "general_operand"))] ;; "" ;; " ;;{ @@ -5819,8 +5819,8 @@ ;; }") (define_expand "movdi" - [(set (match_operand:DI 0 "general_operand" "") - (match_operand:DI 1 "general_operand" ""))] + [(set (match_operand:DI 0 "general_operand") + (match_operand:DI 1 "general_operand"))] "TARGET_EITHER" " if (can_create_pseudo_p ()) @@ -5992,8 +5992,8 @@ ) (define_expand "movsi" - [(set (match_operand:SI 0 "general_operand" "") - (match_operand:SI 1 "general_operand" ""))] + [(set (match_operand:SI 0 "general_operand") + (match_operand:SI 1 "general_operand"))] "TARGET_EITHER" " { @@ -6183,8 +6183,8 @@ ;; ;; Note: Update arm.c: legitimize_pic_address() when changing this pattern. (define_expand "calculate_pic_address" - [(set (match_operand:SI 0 "register_operand" "") - (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") + (mem:SI (plus:SI (match_operand:SI 1 "register_operand") (unspec:SI [(match_operand:SI 2 "" "")] UNSPEC_PIC_SYM))))] "flag_pic" @@ -6474,8 +6474,8 @@ ) (define_expand "storehi_single_op" - [(set (match_operand:HI 0 "memory_operand" "") - (match_operand:HI 1 "general_operand" ""))] + [(set (match_operand:HI 0 "memory_operand") + (match_operand:HI 1 "general_operand"))] "TARGET_32BIT && arm_arch4" " if (!s_register_operand (operands[1], HImode)) @@ -6484,8 +6484,8 @@ ) (define_expand "movhi" - [(set (match_operand:HI 0 "general_operand" "") - (match_operand:HI 1 "general_operand" ""))] + [(set (match_operand:HI 0 "general_operand") + (match_operand:HI 1 "general_operand"))] "TARGET_EITHER" " if (TARGET_ARM) @@ -6709,11 +6709,11 @@ (define_expand "movhi_bigend" [(set (match_dup 2) - (rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "") 0) + (rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand") 0) (const_int 16))) (set (match_dup 3) (ashiftrt:SI (match_dup 2) (const_int 16))) - (set (match_operand:HI 0 "s_register_operand" "") + (set (match_operand:HI 0 "s_register_operand") (match_dup 4))] "TARGET_ARM" " @@ -6766,6 +6766,8 @@ ;; We use a DImode scratch because we may occasionally need an additional ;; temporary if the address isn't offsettable -- push_reload doesn't seem ;; to take any notice of the "o" constraints on reload_memory_operand operand. +;; The reload_in<m> and reload_out<m> patterns require special constraints +;; to be correctly handled in default_secondary_reload function. (define_expand "reload_outhi" [(parallel [(match_operand:HI 0 "arm_reload_memory_operand" "=o") (match_operand:HI 1 "s_register_operand" "r") @@ -6793,8 +6795,8 @@ ") (define_expand "movqi" - [(set (match_operand:QI 0 "general_operand" "") - (match_operand:QI 1 "general_operand" ""))] + [(set (match_operand:QI 0 "general_operand") + (match_operand:QI 1 "general_operand"))] "TARGET_EITHER" " /* Everything except mem = const or mem = mem can be done easily */ @@ -6891,8 +6893,8 @@ ;; HFmode moves (define_expand "movhf" - [(set (match_operand:HF 0 "general_operand" "") - (match_operand:HF 1 "general_operand" ""))] + [(set (match_operand:HF 0 "general_operand") + (match_operand:HF 1 "general_operand"))] "TARGET_EITHER" " if (TARGET_32BIT) @@ -6955,8 +6957,8 @@ ) (define_expand "movsf" - [(set (match_operand:SF 0 "general_operand" "") - (match_operand:SF 1 "general_operand" ""))] + [(set (match_operand:SF 0 "general_operand") + (match_operand:SF 1 "general_operand"))] "TARGET_EITHER" " if (TARGET_32BIT) @@ -7050,8 +7052,8 @@ ) (define_expand "movdf" - [(set (match_operand:DF 0 "general_operand" "") - (match_operand:DF 1 "general_operand" ""))] + [(set (match_operand:DF 0 "general_operand") + (match_operand:DF 1 "general_operand"))] "TARGET_EITHER" " if (TARGET_32BIT) @@ -7087,6 +7089,7 @@ ;; Reloading a df mode value stored in integer regs to memory can require a ;; scratch reg. +;; Another reload_out<m> pattern that requires special constraints. (define_expand "reload_outdf" [(match_operand:DF 0 "arm_reload_memory_operand" "=o") (match_operand:DF 1 "s_register_operand" "r") @@ -7233,10 +7236,10 @@ (define_expand "setmemsi" - [(match_operand:BLK 0 "general_operand" "") - (match_operand:SI 1 "const_int_operand" "") - (match_operand:SI 2 "const_int_operand" "") - (match_operand:SI 3 "const_int_operand" "")] + [(match_operand:BLK 0 "general_operand") + (match_operand:SI 1 "const_int_operand") + (match_operand:SI 2 "const_int_operand") + (match_operand:SI 3 "const_int_operand")] "TARGET_32BIT" { if (arm_gen_setmem (operands)) @@ -7251,10 +7254,10 @@ ;; many registers that there is then probably a better way. (define_expand "cpymemqi" - [(match_operand:BLK 0 "general_operand" "") - (match_operand:BLK 1 "general_operand" "") - (match_operand:SI 2 "const_int_operand" "") - (match_operand:SI 3 "const_int_operand" "")] + [(match_operand:BLK 0 "general_operand") + (match_operand:BLK 1 "general_operand") + (match_operand:SI 2 "const_int_operand") + (match_operand:SI 3 "const_int_operand")] "" " if (TARGET_32BIT) @@ -7304,8 +7307,8 @@ (define_expand "cbranchsi4" [(set (pc) (if_then_else (match_operator 0 "expandable_comparison_operator" - [(match_operand:SI 1 "s_register_operand" "") - (match_operand:SI 2 "nonmemory_operand" "")]) + [(match_operand:SI 1 "s_register_operand") + (match_operand:SI 2 "nonmemory_operand")]) (label_ref (match_operand 3 "" "")) (pc)))] "TARGET_EITHER" @@ -7331,8 +7334,8 @@ (define_expand "cbranchsf4" [(set (pc) (if_then_else (match_operator 0 "expandable_comparison_operator" - [(match_operand:SF 1 "s_register_operand" "") - (match_operand:SF 2 "vfp_compare_operand" "")]) + [(match_operand:SF 1 "s_register_operand") + (match_operand:SF 2 "vfp_compare_operand")]) (label_ref (match_operand 3 "" "")) (pc)))] "TARGET_32BIT && TARGET_HARD_FLOAT" @@ -7343,8 +7346,8 @@ (define_expand "cbranchdf4" [(set (pc) (if_then_else (match_operator 0 "expandable_comparison_operator" - [(match_operand:DF 1 "s_register_operand" "") - (match_operand:DF 2 "vfp_compare_operand" "")]) + [(match_operand:DF 1 "s_register_operand") + (match_operand:DF 2 "vfp_compare_operand")]) (label_ref (match_operand 3 "" "")) (pc)))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" @@ -7355,8 +7358,8 @@ (define_expand "cbranchdi4" [(set (pc) (if_then_else (match_operator 0 "expandable_comparison_operator" - [(match_operand:DI 1 "s_register_operand" "") - (match_operand:DI 2 "cmpdi_operand" "")]) + [(match_operand:DI 1 "s_register_operand") + (match_operand:DI 2 "cmpdi_operand")]) (label_ref (match_operand 3 "" "")) (pc)))] "TARGET_32BIT" @@ -7608,7 +7611,7 @@ ; scc insns (define_expand "cstore_cc" - [(set (match_operand:SI 0 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand") (match_operator:SI 1 "" [(match_operand 2 "" "") (match_operand 3 "" "")]))] "TARGET_32BIT" @@ -7674,10 +7677,10 @@ ) (define_expand "cstoresi4" - [(set (match_operand:SI 0 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand") (match_operator:SI 1 "expandable_comparison_operator" - [(match_operand:SI 2 "s_register_operand" "") - (match_operand:SI 3 "reg_or_int_operand" "")]))] + [(match_operand:SI 2 "s_register_operand") + (match_operand:SI 3 "reg_or_int_operand")]))] "TARGET_32BIT || TARGET_THUMB1" "{ rtx op3, scratch, scratch2; @@ -7828,30 +7831,30 @@ ) (define_expand "cstoresf4" - [(set (match_operand:SI 0 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand") (match_operator:SI 1 "expandable_comparison_operator" - [(match_operand:SF 2 "s_register_operand" "") - (match_operand:SF 3 "vfp_compare_operand" "")]))] + [(match_operand:SF 2 "s_register_operand") + (match_operand:SF 3 "vfp_compare_operand")]))] "TARGET_32BIT && TARGET_HARD_FLOAT" "emit_insn (gen_cstore_cc (operands[0], operands[1], operands[2], operands[3])); DONE;" ) (define_expand "cstoredf4" - [(set (match_operand:SI 0 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand") (match_operator:SI 1 "expandable_comparison_operator" - [(match_operand:DF 2 "s_register_operand" "") - (match_operand:DF 3 "vfp_compare_operand" "")]))] + [(match_operand:DF 2 "s_register_operand") + (match_operand:DF 3 "vfp_compare_operand")]))] "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE" "emit_insn (gen_cstore_cc (operands[0], operands[1], operands[2], operands[3])); DONE;" ) (define_expand "cstoredi4" - [(set (match_operand:SI 0 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand") (match_operator:SI 1 "expandable_comparison_operator" - [(match_operand:DI 2 "s_register_operand" "") - (match_operand:DI 3 "cmpdi_operand" "")]))] + [(match_operand:DI 2 "s_register_operand") + (match_operand:DI 3 "cmpdi_operand")]))] "TARGET_32BIT" "{ if (!arm_validize_comparison (&operands[1], @@ -7868,10 +7871,10 @@ ;; Conditional move insns (define_expand "movsicc" - [(set (match_operand:SI 0 "s_register_operand" "") - (if_then_else:SI (match_operand 1 "expandable_comparison_operator" "") - (match_operand:SI 2 "arm_not_operand" "") - (match_operand:SI 3 "arm_not_operand" "")))] + [(set (match_operand:SI 0 "s_register_operand") + (if_then_else:SI (match_operand 1 "expandable_comparison_operator") + (match_operand:SI 2 "arm_not_operand") + (match_operand:SI 3 "arm_not_operand")))] "TARGET_32BIT" " { @@ -7912,10 +7915,10 @@ ) (define_expand "movsfcc" - [(set (match_operand:SF 0 "s_register_operand" "") - (if_then_else:SF (match_operand 1 "arm_cond_move_operator" "") - (match_operand:SF 2 "s_register_operand" "") - (match_operand:SF 3 "s_register_operand" "")))] + [(set (match_operand:SF 0 "s_register_operand") + (if_then_else:SF (match_operand 1 "arm_cond_move_operator") + (match_operand:SF 2 "s_register_operand") + (match_operand:SF 3 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT" " { @@ -7934,10 +7937,10 @@ ) (define_expand "movdfcc" - [(set (match_operand:DF 0 "s_register_operand" "") - (if_then_else:DF (match_operand 1 "arm_cond_move_operator" "") - (match_operand:DF 2 "s_register_operand" "") - (match_operand:DF 3 "s_register_operand" "")))] + [(set (match_operand:DF 0 "s_register_operand") + (if_then_else:DF (match_operand 1 "arm_cond_move_operator") + (match_operand:DF 2 "s_register_operand") + (match_operand:DF 3 "s_register_operand")))] "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE" " { @@ -8133,8 +8136,8 @@ ) (define_expand "call" - [(parallel [(call (match_operand 0 "memory_operand" "") - (match_operand 1 "general_operand" "")) + [(parallel [(call (match_operand 0 "memory_operand") + (match_operand 1 "general_operand")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))])] "TARGET_EITHER" @@ -8172,15 +8175,15 @@ ) (define_expand "call_internal" - [(parallel [(call (match_operand 0 "memory_operand" "") - (match_operand 1 "general_operand" "")) + [(parallel [(call (match_operand 0 "memory_operand") + (match_operand 1 "general_operand")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))])]) (define_expand "nonsecure_call_internal" - [(parallel [(call (unspec:SI [(match_operand 0 "memory_operand" "")] + [(parallel [(call (unspec:SI [(match_operand 0 "memory_operand")] UNSPEC_NONSECURE_MEM) - (match_operand 1 "general_operand" "")) + (match_operand 1 "general_operand")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))])] "use_cmse" @@ -8221,8 +8224,8 @@ (define_expand "call_value" [(parallel [(set (match_operand 0 "" "") - (call (match_operand 1 "memory_operand" "") - (match_operand 2 "general_operand" ""))) + (call (match_operand 1 "memory_operand") + (match_operand 2 "general_operand"))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))])] "TARGET_EITHER" @@ -8262,16 +8265,16 @@ (define_expand "call_value_internal" [(parallel [(set (match_operand 0 "" "") - (call (match_operand 1 "memory_operand" "") - (match_operand 2 "general_operand" ""))) + (call (match_operand 1 "memory_operand") + (match_operand 2 "general_operand"))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))])]) (define_expand "nonsecure_call_value_internal" [(parallel [(set (match_operand 0 "" "") - (call (unspec:SI [(match_operand 1 "memory_operand" "")] + (call (unspec:SI [(match_operand 1 "memory_operand")] UNSPEC_NONSECURE_MEM) - (match_operand 2 "general_operand" ""))) + (match_operand 2 "general_operand"))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))])] "use_cmse" @@ -8361,15 +8364,15 @@ ) (define_expand "sibcall_internal" - [(parallel [(call (match_operand 0 "memory_operand" "") - (match_operand 1 "general_operand" "")) + [(parallel [(call (match_operand 0 "memory_operand") + (match_operand 1 "general_operand")) (return) (use (match_operand 2 "" ""))])]) ;; We may also be able to do sibcalls for Thumb, but it's much harder... (define_expand "sibcall" - [(parallel [(call (match_operand 0 "memory_operand" "") - (match_operand 1 "general_operand" "")) + [(parallel [(call (match_operand 0 "memory_operand") + (match_operand 1 "general_operand")) (return) (use (match_operand 2 "" ""))])] "TARGET_32BIT" @@ -8394,15 +8397,15 @@ (define_expand "sibcall_value_internal" [(parallel [(set (match_operand 0 "" "") - (call (match_operand 1 "memory_operand" "") - (match_operand 2 "general_operand" ""))) + (call (match_operand 1 "memory_operand") + (match_operand 2 "general_operand"))) (return) (use (match_operand 3 "" ""))])]) (define_expand "sibcall_value" [(parallel [(set (match_operand 0 "" "") - (call (match_operand 1 "memory_operand" "") - (match_operand 2 "general_operand" ""))) + (call (match_operand 1 "memory_operand") + (match_operand 2 "general_operand"))) (return) (use (match_operand 3 "" ""))])] "TARGET_32BIT" @@ -8571,7 +8574,7 @@ [(set (match_dup 1) (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) (const_int 0))) - (set (match_operand:SI 0 "s_register_operand" "") + (set (match_operand:SI 0 "s_register_operand") (if_then_else:SI (eq (match_dup 1) (const_int 0)) (const_int -1) (const_int 67108860)))] ; 0x03fffffc @@ -8663,7 +8666,7 @@ ) (define_expand "untyped_return" - [(match_operand:BLK 0 "memory_operand" "") + [(match_operand:BLK 0 "memory_operand") (match_operand 1 "" "")] "TARGET_EITHER" " @@ -8749,8 +8752,8 @@ ;; Named patterns for stack smashing protection. (define_expand "stack_protect_combined_set" [(parallel - [(set (match_operand:SI 0 "memory_operand" "") - (unspec:SI [(match_operand:SI 1 "guard_operand" "")] + [(set (match_operand:SI 0 "memory_operand") + (unspec:SI [(match_operand:SI 1 "guard_operand")] UNSPEC_SP_SET)) (clobber (match_scratch:SI 2 "")) (clobber (match_scratch:SI 3 ""))])] @@ -8816,8 +8819,8 @@ [(parallel [(set (pc) (if_then_else - (eq (match_operand:SI 0 "memory_operand" "") - (unspec:SI [(match_operand:SI 1 "guard_operand" "")] + (eq (match_operand:SI 0 "memory_operand") + (unspec:SI [(match_operand:SI 1 "guard_operand")] UNSPEC_SP_TEST)) (label_ref (match_operand 2)) (pc))) @@ -8905,9 +8908,9 @@ ) (define_expand "casesi" - [(match_operand:SI 0 "s_register_operand" "") ; index to jump on - (match_operand:SI 1 "const_int_operand" "") ; lower bound - (match_operand:SI 2 "const_int_operand" "") ; total range + [(match_operand:SI 0 "s_register_operand") ; index to jump on + (match_operand:SI 1 "const_int_operand") ; lower bound + (match_operand:SI 2 "const_int_operand") ; total range (match_operand:SI 3 "" "") ; table label (match_operand:SI 4 "" "")] ; Out of range label "(TARGET_32BIT || optimize_size || flag_pic) && !target_pure_code" @@ -8986,7 +8989,7 @@ (define_expand "indirect_jump" [(set (pc) - (match_operand:SI 0 "s_register_operand" ""))] + (match_operand:SI 0 "s_register_operand"))] "TARGET_EITHER" " /* Thumb-2 doesn't have mov pc, reg. Explicitly set the low bit of the @@ -11041,9 +11044,9 @@ ) (define_expand "eh_epilogue" - [(use (match_operand:SI 0 "register_operand" "")) - (use (match_operand:SI 1 "register_operand" "")) - (use (match_operand:SI 2 "register_operand" ""))] + [(use (match_operand:SI 0 "register_operand")) + (use (match_operand:SI 1 "register_operand")) + (use (match_operand:SI 2 "register_operand"))] "TARGET_EITHER" " { @@ -11628,7 +11631,7 @@ ;; Patterns for exception handling (define_expand "eh_return" - [(use (match_operand 0 "general_operand" ""))] + [(use (match_operand 0 "general_operand"))] "TARGET_EITHER" " { @@ -11702,7 +11705,7 @@ ;; For thread pointer builtin (define_expand "get_thread_pointersi" - [(match_operand:SI 0 "s_register_operand" "=r")] + [(match_operand:SI 0 "s_register_operand")] "" " { @@ -11744,20 +11747,20 @@ ) (define_expand "arm_legacy_rev" - [(set (match_operand:SI 2 "s_register_operand" "") - (xor:SI (rotatert:SI (match_operand:SI 1 "s_register_operand" "") + [(set (match_operand:SI 2 "s_register_operand") + (xor:SI (rotatert:SI (match_operand:SI 1 "s_register_operand") (const_int 16)) (match_dup 1))) (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 8))) - (set (match_operand:SI 3 "s_register_operand" "") + (set (match_operand:SI 3 "s_register_operand") (rotatert:SI (match_dup 1) (const_int 8))) (set (match_dup 2) (and:SI (match_dup 2) (const_int -65281))) - (set (match_operand:SI 0 "s_register_operand" "") + (set (match_operand:SI 0 "s_register_operand") (xor:SI (match_dup 3) (match_dup 2)))] "TARGET_32BIT" @@ -11766,18 +11769,18 @@ ;; Reuse temporaries to keep register pressure down. (define_expand "thumb_legacy_rev" - [(set (match_operand:SI 2 "s_register_operand" "") - (ashift:SI (match_operand:SI 1 "s_register_operand" "") + [(set (match_operand:SI 2 "s_register_operand") + (ashift:SI (match_operand:SI 1 "s_register_operand") (const_int 24))) - (set (match_operand:SI 3 "s_register_operand" "") + (set (match_operand:SI 3 "s_register_operand") (lshiftrt:SI (match_dup 1) (const_int 24))) (set (match_dup 3) (ior:SI (match_dup 3) (match_dup 2))) - (set (match_operand:SI 4 "s_register_operand" "") + (set (match_operand:SI 4 "s_register_operand") (const_int 16)) - (set (match_operand:SI 5 "s_register_operand" "") + (set (match_operand:SI 5 "s_register_operand") (rotatert:SI (match_dup 1) (match_dup 4))) (set (match_dup 2) @@ -11792,7 +11795,7 @@ (set (match_dup 5) (rotatert:SI (match_dup 5) (match_dup 4))) - (set (match_operand:SI 0 "s_register_operand" "") + (set (match_operand:SI 0 "s_register_operand") (ior:SI (match_dup 5) (match_dup 3)))] "TARGET_THUMB" @@ -11808,9 +11811,9 @@ ;; rsbpl r0, r1, #0 (define_expand "modsi3" - [(match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "const_int_operand" "")] + [(match_operand:SI 0 "register_operand") + (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "const_int_operand")] "TARGET_32BIT" { HOST_WIDE_INT val = INTVAL (operands[2]); @@ -11869,8 +11872,8 @@ ) (define_expand "bswapsi2" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))] + [(set (match_operand:SI 0 "s_register_operand") + (bswap:SI (match_operand:SI 1 "s_register_operand")))] "TARGET_EITHER && (arm_arch6 || !optimize_size)" " if (!arm_arch6) @@ -11965,8 +11968,8 @@ ) (define_expand "bswaphi2" - [(set (match_operand:HI 0 "s_register_operand" "=r") - (bswap:HI (match_operand:HI 1 "s_register_operand" "r")))] + [(set (match_operand:HI 0 "s_register_operand") + (bswap:HI (match_operand:HI 1 "s_register_operand")))] "arm_arch6" "" ) diff --git a/gcc/config/arm/iwmmxt.md b/gcc/config/arm/iwmmxt.md index 65f9b32..310019a 100644 --- a/gcc/config/arm/iwmmxt.md +++ b/gcc/config/arm/iwmmxt.md @@ -256,55 +256,55 @@ (define_expand "iwmmxt_setwcgr0" [(set (reg:SI WCGR0) - (match_operand:SI 0 "register_operand" ""))] + (match_operand:SI 0 "register_operand"))] "TARGET_REALLY_IWMMXT" {} ) (define_expand "iwmmxt_setwcgr1" [(set (reg:SI WCGR1) - (match_operand:SI 0 "register_operand" ""))] + (match_operand:SI 0 "register_operand"))] "TARGET_REALLY_IWMMXT" {} ) (define_expand "iwmmxt_setwcgr2" [(set (reg:SI WCGR2) - (match_operand:SI 0 "register_operand" ""))] + (match_operand:SI 0 "register_operand"))] "TARGET_REALLY_IWMMXT" {} ) (define_expand "iwmmxt_setwcgr3" [(set (reg:SI WCGR3) - (match_operand:SI 0 "register_operand" ""))] + (match_operand:SI 0 "register_operand"))] "TARGET_REALLY_IWMMXT" {} ) (define_expand "iwmmxt_getwcgr0" - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (reg:SI WCGR0))] "TARGET_REALLY_IWMMXT" {} ) (define_expand "iwmmxt_getwcgr1" - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (reg:SI WCGR1))] "TARGET_REALLY_IWMMXT" {} ) (define_expand "iwmmxt_getwcgr2" - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (reg:SI WCGR2))] "TARGET_REALLY_IWMMXT" {} ) (define_expand "iwmmxt_getwcgr3" - [(set (match_operand:SI 0 "register_operand" "") + [(set (match_operand:SI 0 "register_operand") (reg:SI WCGR3))] "TARGET_REALLY_IWMMXT" {} diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index bcf838f..4bfe770 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -123,8 +123,8 @@ sub-reg and may ICE if it can't. */ (define_expand "movti" - [(set (match_operand:TI 0 "nonimmediate_operand" "") - (match_operand:TI 1 "general_operand" ""))] + [(set (match_operand:TI 0 "nonimmediate_operand") + (match_operand:TI 1 "general_operand"))] "TARGET_NEON" { if (can_create_pseudo_p ()) @@ -135,8 +135,8 @@ }) (define_expand "mov<mode>" - [(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "") - (match_operand:VSTRUCT 1 "general_operand" ""))] + [(set (match_operand:VSTRUCT 0 "nonimmediate_operand") + (match_operand:VSTRUCT 1 "general_operand"))] "TARGET_NEON" { if (can_create_pseudo_p ()) @@ -392,9 +392,9 @@ ) (define_expand "vec_set<mode>" - [(match_operand:VDQ 0 "s_register_operand" "") - (match_operand:<V_elem> 1 "s_register_operand" "") - (match_operand:SI 2 "immediate_operand" "")] + [(match_operand:VDQ 0 "s_register_operand") + (match_operand:<V_elem> 1 "s_register_operand") + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { HOST_WIDE_INT elem = HOST_WIDE_INT_1 << INTVAL (operands[2]); @@ -471,7 +471,7 @@ ) (define_expand "vec_init<mode><V_elem_l>" - [(match_operand:VDQ 0 "s_register_operand" "") + [(match_operand:VDQ 0 "s_register_operand") (match_operand 1 "" "")] "TARGET_NEON" { @@ -628,9 +628,9 @@ and disabled for -Os since it increases code size . */ (define_expand "div<mode>3" - [(set (match_operand:VCVTF 0 "s_register_operand" "=w") - (div:VCVTF (match_operand:VCVTF 1 "s_register_operand" "w") - (match_operand:VCVTF 2 "s_register_operand" "w")))] + [(set (match_operand:VCVTF 0 "s_register_operand") + (div:VCVTF (match_operand:VCVTF 1 "s_register_operand") + (match_operand:VCVTF 2 "s_register_operand")))] "TARGET_NEON && !optimize_size && flag_reciprocal_math" { @@ -1138,9 +1138,9 @@ ) (define_expand "vashr<mode>3" - [(set (match_operand:VDQIW 0 "s_register_operand" "") - (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "") - (match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))] + [(set (match_operand:VDQIW 0 "s_register_operand") + (ashiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") + (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] "TARGET_NEON" { if (s_register_operand (operands[2], <MODE>mode)) @@ -1155,9 +1155,9 @@ }) (define_expand "vlshr<mode>3" - [(set (match_operand:VDQIW 0 "s_register_operand" "") - (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand" "") - (match_operand:VDQIW 2 "imm_rshift_or_reg_neon" "")))] + [(set (match_operand:VDQIW 0 "s_register_operand") + (lshiftrt:VDQIW (match_operand:VDQIW 1 "s_register_operand") + (match_operand:VDQIW 2 "imm_rshift_or_reg_neon")))] "TARGET_NEON" { if (s_register_operand (operands[2], <MODE>mode)) @@ -1359,11 +1359,11 @@ ;; Widening operations (define_expand "widen_ssum<mode>3" - [(set (match_operand:<V_double_width> 0 "s_register_operand" "") + [(set (match_operand:<V_double_width> 0 "s_register_operand") (plus:<V_double_width> (sign_extend:<V_double_width> - (match_operand:VQI 1 "s_register_operand" "")) - (match_operand:<V_double_width> 2 "s_register_operand" "")))] + (match_operand:VQI 1 "s_register_operand")) + (match_operand:<V_double_width> 2 "s_register_operand")))] "TARGET_NEON" { machine_mode mode = GET_MODE (operands[1]); @@ -1429,11 +1429,11 @@ ) (define_expand "widen_usum<mode>3" - [(set (match_operand:<V_double_width> 0 "s_register_operand" "") + [(set (match_operand:<V_double_width> 0 "s_register_operand") (plus:<V_double_width> (zero_extend:<V_double_width> - (match_operand:VQI 1 "s_register_operand" "")) - (match_operand:<V_double_width> 2 "s_register_operand" "")))] + (match_operand:VQI 1 "s_register_operand")) + (match_operand:<V_double_width> 2 "s_register_operand")))] "TARGET_NEON" { machine_mode mode = GET_MODE (operands[1]); @@ -1564,8 +1564,8 @@ ) (define_expand "move_hi_quad_<mode>" - [(match_operand:ANY128 0 "s_register_operand" "") - (match_operand:<V_HALF> 1 "s_register_operand" "")] + [(match_operand:ANY128 0 "s_register_operand") + (match_operand:<V_HALF> 1 "s_register_operand")] "TARGET_NEON" { emit_move_insn (simplify_gen_subreg (<V_HALF>mode, operands[0], <MODE>mode, @@ -1575,8 +1575,8 @@ }) (define_expand "move_lo_quad_<mode>" - [(match_operand:ANY128 0 "s_register_operand" "") - (match_operand:<V_HALF> 1 "s_register_operand" "")] + [(match_operand:ANY128 0 "s_register_operand") + (match_operand:<V_HALF> 1 "s_register_operand")] "TARGET_NEON" { emit_move_insn (simplify_gen_subreg (<V_HALF>mode, operands[0], @@ -1588,8 +1588,8 @@ ;; Reduction operations (define_expand "reduc_plus_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VD 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VD 1 "s_register_operand")] "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" { rtx vec = gen_reg_rtx (<MODE>mode); @@ -1601,8 +1601,8 @@ }) (define_expand "reduc_plus_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VQ 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VQ 1 "s_register_operand")] "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations) && !BYTES_BIG_ENDIAN" { @@ -1615,8 +1615,8 @@ }) (define_expand "reduc_plus_scal_v2di" - [(match_operand:DI 0 "nonimmediate_operand" "=w") - (match_operand:V2DI 1 "s_register_operand" "")] + [(match_operand:DI 0 "nonimmediate_operand") + (match_operand:V2DI 1 "s_register_operand")] "TARGET_NEON && !BYTES_BIG_ENDIAN" { rtx vec = gen_reg_rtx (V2DImode); @@ -1637,8 +1637,8 @@ ) (define_expand "reduc_smin_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VD 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VD 1 "s_register_operand")] "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" { rtx vec = gen_reg_rtx (<MODE>mode); @@ -1651,8 +1651,8 @@ }) (define_expand "reduc_smin_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VQ 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VQ 1 "s_register_operand")] "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations) && !BYTES_BIG_ENDIAN" { @@ -1665,8 +1665,8 @@ }) (define_expand "reduc_smax_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VD 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VD 1 "s_register_operand")] "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" { rtx vec = gen_reg_rtx (<MODE>mode); @@ -1678,8 +1678,8 @@ }) (define_expand "reduc_smax_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VQ 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VQ 1 "s_register_operand")] "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations) && !BYTES_BIG_ENDIAN" { @@ -1692,8 +1692,8 @@ }) (define_expand "reduc_umin_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VDI 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VDI 1 "s_register_operand")] "TARGET_NEON" { rtx vec = gen_reg_rtx (<MODE>mode); @@ -1705,8 +1705,8 @@ }) (define_expand "reduc_umin_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VQI 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VQI 1 "s_register_operand")] "TARGET_NEON && !BYTES_BIG_ENDIAN" { rtx step1 = gen_reg_rtx (<V_HALF>mode); @@ -1718,8 +1718,8 @@ }) (define_expand "reduc_umax_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VDI 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VDI 1 "s_register_operand")] "TARGET_NEON" { rtx vec = gen_reg_rtx (<MODE>mode); @@ -1731,8 +1731,8 @@ }) (define_expand "reduc_umax_scal_<mode>" - [(match_operand:<V_elem> 0 "nonimmediate_operand" "") - (match_operand:VQI 1 "s_register_operand" "")] + [(match_operand:<V_elem> 0 "nonimmediate_operand") + (match_operand:VQI 1 "s_register_operand")] "TARGET_NEON && !BYTES_BIG_ENDIAN" { rtx step1 = gen_reg_rtx (<V_HALF>mode); @@ -1867,13 +1867,13 @@ ;; element-wise. (define_expand "vcond<mode><mode>" - [(set (match_operand:VDQW 0 "s_register_operand" "") + [(set (match_operand:VDQW 0 "s_register_operand") (if_then_else:VDQW (match_operator 3 "comparison_operator" - [(match_operand:VDQW 4 "s_register_operand" "") - (match_operand:VDQW 5 "nonmemory_operand" "")]) - (match_operand:VDQW 1 "s_register_operand" "") - (match_operand:VDQW 2 "s_register_operand" "")))] + [(match_operand:VDQW 4 "s_register_operand") + (match_operand:VDQW 5 "nonmemory_operand")]) + (match_operand:VDQW 1 "s_register_operand") + (match_operand:VDQW 2 "s_register_operand")))] "TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)" { int inverse = 0; @@ -2032,13 +2032,13 @@ }) (define_expand "vcondu<mode><mode>" - [(set (match_operand:VDQIW 0 "s_register_operand" "") + [(set (match_operand:VDQIW 0 "s_register_operand") (if_then_else:VDQIW (match_operator 3 "arm_comparison_operator" - [(match_operand:VDQIW 4 "s_register_operand" "") - (match_operand:VDQIW 5 "s_register_operand" "")]) - (match_operand:VDQIW 1 "s_register_operand" "") - (match_operand:VDQIW 2 "s_register_operand" "")))] + [(match_operand:VDQIW 4 "s_register_operand") + (match_operand:VDQIW 5 "s_register_operand")]) + (match_operand:VDQIW 1 "s_register_operand") + (match_operand:VDQIW 2 "s_register_operand")))] "TARGET_NEON" { rtx mask; @@ -2103,9 +2103,9 @@ ; good for plain vadd, vaddq. (define_expand "neon_vadd<mode>" - [(match_operand:VCVTF 0 "s_register_operand" "=w") - (match_operand:VCVTF 1 "s_register_operand" "w") - (match_operand:VCVTF 2 "s_register_operand" "w")] + [(match_operand:VCVTF 0 "s_register_operand") + (match_operand:VCVTF 1 "s_register_operand") + (match_operand:VCVTF 2 "s_register_operand")] "TARGET_NEON" { if (!<Is_float_mode> || flag_unsafe_math_optimizations) @@ -2250,10 +2250,10 @@ ) (define_expand "neon_vmla<mode>" - [(match_operand:VDQW 0 "s_register_operand" "=w") - (match_operand:VDQW 1 "s_register_operand" "0") - (match_operand:VDQW 2 "s_register_operand" "w") - (match_operand:VDQW 3 "s_register_operand" "w")] + [(match_operand:VDQW 0 "s_register_operand") + (match_operand:VDQW 1 "s_register_operand") + (match_operand:VDQW 2 "s_register_operand") + (match_operand:VDQW 3 "s_register_operand")] "TARGET_NEON" { if (!<Is_float_mode> || flag_unsafe_math_optimizations) @@ -2741,10 +2741,10 @@ ) (define_expand "neon_vmls<mode>" - [(match_operand:VDQW 0 "s_register_operand" "=w") - (match_operand:VDQW 1 "s_register_operand" "0") - (match_operand:VDQW 2 "s_register_operand" "w") - (match_operand:VDQW 3 "s_register_operand" "w")] + [(match_operand:VDQW 0 "s_register_operand") + (match_operand:VDQW 1 "s_register_operand") + (match_operand:VDQW 2 "s_register_operand") + (match_operand:VDQW 3 "s_register_operand")] "TARGET_NEON" { if (!<Is_float_mode> || flag_unsafe_math_optimizations) @@ -2849,9 +2849,9 @@ ) (define_expand "neon_vsub<mode>" - [(match_operand:VCVTF 0 "s_register_operand" "=w") - (match_operand:VCVTF 1 "s_register_operand" "w") - (match_operand:VCVTF 2 "s_register_operand" "w")] + [(match_operand:VCVTF 0 "s_register_operand") + (match_operand:VCVTF 1 "s_register_operand") + (match_operand:VCVTF 2 "s_register_operand")] "TARGET_NEON" { if (!<Is_float_mode> || flag_unsafe_math_optimizations) @@ -2930,10 +2930,10 @@ ;; These may expand to an UNSPEC pattern when a floating point mode is used ;; without unsafe math optimizations. (define_expand "neon_vc<cmp_op><mode>" - [(match_operand:<V_cmp_result> 0 "s_register_operand" "=w,w") + [(match_operand:<V_cmp_result> 0 "s_register_operand") (neg:<V_cmp_result> - (COMPARISONS:VDQW (match_operand:VDQW 1 "s_register_operand" "w,w") - (match_operand:VDQW 2 "reg_or_zero_operand" "w,Dz")))] + (COMPARISONS:VDQW (match_operand:VDQW 1 "s_register_operand") + (match_operand:VDQW 2 "reg_or_zero_operand")))] "TARGET_NEON" { /* For FP comparisons use UNSPECS unless -funsafe-math-optimizations @@ -3359,9 +3359,9 @@ ) (define_expand "neon_vpadd<mode>" - [(match_operand:VD 0 "s_register_operand" "=w") - (match_operand:VD 1 "s_register_operand" "w") - (match_operand:VD 2 "s_register_operand" "w")] + [(match_operand:VD 0 "s_register_operand") + (match_operand:VD 1 "s_register_operand") + (match_operand:VD 2 "s_register_operand")] "TARGET_NEON" { emit_insn (gen_neon_vpadd_internal<mode> (operands[0], operands[1], @@ -3451,8 +3451,8 @@ ) (define_expand "neon_vabs<mode>" - [(match_operand:VDQW 0 "s_register_operand" "") - (match_operand:VDQW 1 "s_register_operand" "")] + [(match_operand:VDQW 0 "s_register_operand") + (match_operand:VDQW 1 "s_register_operand")] "TARGET_NEON" { emit_insn (gen_abs<mode>2 (operands[0], operands[1])); @@ -3477,8 +3477,8 @@ ) (define_expand "neon_vneg<mode>" - [(match_operand:VDQW 0 "s_register_operand" "") - (match_operand:VDQW 1 "s_register_operand" "")] + [(match_operand:VDQW 0 "s_register_operand") + (match_operand:VDQW 1 "s_register_operand")] "TARGET_NEON" { emit_insn (gen_neg<mode>2 (operands[0], operands[1])); @@ -3678,8 +3678,8 @@ ) (define_expand "neon_vclz<mode>" - [(match_operand:VDQIW 0 "s_register_operand" "") - (match_operand:VDQIW 1 "s_register_operand" "")] + [(match_operand:VDQIW 0 "s_register_operand") + (match_operand:VDQIW 1 "s_register_operand")] "TARGET_NEON" { emit_insn (gen_clz<mode>2 (operands[0], operands[1])); @@ -3695,8 +3695,8 @@ ) (define_expand "neon_vcnt<mode>" - [(match_operand:VE 0 "s_register_operand" "=w") - (match_operand:VE 1 "s_register_operand" "w")] + [(match_operand:VE 0 "s_register_operand") + (match_operand:VE 1 "s_register_operand")] "TARGET_NEON" { emit_insn (gen_popcount<mode>2 (operands[0], operands[1])); @@ -3731,8 +3731,8 @@ ) (define_expand "neon_vmvn<mode>" - [(match_operand:VDQIW 0 "s_register_operand" "") - (match_operand:VDQIW 1 "s_register_operand" "")] + [(match_operand:VDQIW 0 "s_register_operand") + (match_operand:VDQIW 1 "s_register_operand")] "TARGET_NEON" { emit_insn (gen_one_cmpl<mode>2 (operands[0], operands[1])); @@ -3832,9 +3832,9 @@ ) (define_expand "neon_vget_lane<mode>" - [(match_operand:<V_ext> 0 "s_register_operand" "") - (match_operand:VDQW 1 "s_register_operand" "") - (match_operand:SI 2 "immediate_operand" "")] + [(match_operand:<V_ext> 0 "s_register_operand") + (match_operand:VDQW 1 "s_register_operand") + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { if (BYTES_BIG_ENDIAN) @@ -3862,9 +3862,9 @@ }) (define_expand "neon_vget_laneu<mode>" - [(match_operand:<V_ext> 0 "s_register_operand" "") - (match_operand:VDQIW 1 "s_register_operand" "") - (match_operand:SI 2 "immediate_operand" "")] + [(match_operand:<V_ext> 0 "s_register_operand") + (match_operand:VDQIW 1 "s_register_operand") + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { if (BYTES_BIG_ENDIAN) @@ -3892,9 +3892,9 @@ }) (define_expand "neon_vget_lanedi" - [(match_operand:DI 0 "s_register_operand" "=r") - (match_operand:DI 1 "s_register_operand" "w") - (match_operand:SI 2 "immediate_operand" "")] + [(match_operand:DI 0 "s_register_operand") + (match_operand:DI 1 "s_register_operand") + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { emit_move_insn (operands[0], operands[1]); @@ -3902,9 +3902,9 @@ }) (define_expand "neon_vget_lanev2di" - [(match_operand:DI 0 "s_register_operand" "") - (match_operand:V2DI 1 "s_register_operand" "") - (match_operand:SI 2 "immediate_operand" "")] + [(match_operand:DI 0 "s_register_operand") + (match_operand:V2DI 1 "s_register_operand") + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { int lane; @@ -3931,10 +3931,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vset_lane<mode>" - [(match_operand:VDQ 0 "s_register_operand" "=w") - (match_operand:<V_elem> 1 "s_register_operand" "r") - (match_operand:VDQ 2 "s_register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i")] + [(match_operand:VDQ 0 "s_register_operand") + (match_operand:<V_elem> 1 "s_register_operand") + (match_operand:VDQ 2 "s_register_operand") + (match_operand:SI 3 "immediate_operand")] "TARGET_NEON" { unsigned int elt = INTVAL (operands[3]); @@ -3954,10 +3954,10 @@ if (BYTES_BIG_ENDIAN) ; See neon_vget_lanedi comment for reasons operands 2 & 3 are ignored. (define_expand "neon_vset_lanedi" - [(match_operand:DI 0 "s_register_operand" "=w") - (match_operand:DI 1 "s_register_operand" "r") - (match_operand:DI 2 "s_register_operand" "0") - (match_operand:SI 3 "immediate_operand" "i")] + [(match_operand:DI 0 "s_register_operand") + (match_operand:DI 1 "s_register_operand") + (match_operand:DI 2 "s_register_operand") + (match_operand:SI 3 "immediate_operand")] "TARGET_NEON" { emit_move_insn (operands[0], operands[1]); @@ -3965,8 +3965,8 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vcreate<mode>" - [(match_operand:VD_RE 0 "s_register_operand" "") - (match_operand:DI 1 "general_operand" "")] + [(match_operand:VD_RE 0 "s_register_operand") + (match_operand:DI 1 "general_operand")] "TARGET_NEON" { rtx src = gen_lowpart (<MODE>mode, operands[1]); @@ -4009,8 +4009,8 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "neon_vdup_ndi" - [(match_operand:DI 0 "s_register_operand" "=w") - (match_operand:DI 1 "s_register_operand" "r")] + [(match_operand:DI 0 "s_register_operand") + (match_operand:DI 1 "s_register_operand")] "TARGET_NEON" { emit_move_insn (operands[0], operands[1]); @@ -4074,9 +4074,9 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "neon_vdup_lane<mode>" - [(match_operand:VDQW 0 "s_register_operand" "=w") - (match_operand:<V_double_vector_mode> 1 "s_register_operand" "w") - (match_operand:SI 2 "immediate_operand" "i")] + [(match_operand:VDQW 0 "s_register_operand") + (match_operand:<V_double_vector_mode> 1 "s_register_operand") + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { if (BYTES_BIG_ENDIAN) @@ -4113,9 +4113,9 @@ if (BYTES_BIG_ENDIAN) ; Scalar index is ignored, since only zero is valid here. (define_expand "neon_vdup_lanedi" - [(match_operand:DI 0 "s_register_operand" "=w") - (match_operand:DI 1 "s_register_operand" "w") - (match_operand:SI 2 "immediate_operand" "i")] + [(match_operand:DI 0 "s_register_operand") + (match_operand:DI 1 "s_register_operand") + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { emit_move_insn (operands[0], operands[1]); @@ -4124,9 +4124,9 @@ if (BYTES_BIG_ENDIAN) ; Likewise for v2di, as the DImode second operand has only a single element. (define_expand "neon_vdup_lanev2di" - [(match_operand:V2DI 0 "s_register_operand" "=w") - (match_operand:DI 1 "s_register_operand" "w") - (match_operand:SI 2 "immediate_operand" "i")] + [(match_operand:V2DI 0 "s_register_operand") + (match_operand:DI 1 "s_register_operand") + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { emit_insn (gen_neon_vdup_nv2di (operands[0], operands[1])); @@ -4655,9 +4655,9 @@ if (BYTES_BIG_ENDIAN) ; using vld1_lane, but that hasn't been done yet. (define_expand "neon_vmul_n<mode>" - [(match_operand:VMD 0 "s_register_operand" "") - (match_operand:VMD 1 "s_register_operand" "") - (match_operand:<V_elem> 2 "s_register_operand" "")] + [(match_operand:VMD 0 "s_register_operand") + (match_operand:VMD 1 "s_register_operand") + (match_operand:<V_elem> 2 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4668,9 +4668,9 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmul_n<mode>" - [(match_operand:VMQ 0 "s_register_operand" "") - (match_operand:VMQ 1 "s_register_operand" "") - (match_operand:<V_elem> 2 "s_register_operand" "")] + [(match_operand:VMQ 0 "s_register_operand") + (match_operand:VMQ 1 "s_register_operand") + (match_operand:<V_elem> 2 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<V_HALF>mode); @@ -4694,9 +4694,9 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmulls_n<mode>" - [(match_operand:<V_widen> 0 "s_register_operand" "") - (match_operand:VMDI 1 "s_register_operand" "") - (match_operand:<V_elem> 2 "s_register_operand" "")] + [(match_operand:<V_widen> 0 "s_register_operand") + (match_operand:VMDI 1 "s_register_operand") + (match_operand:<V_elem> 2 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4707,9 +4707,9 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmullu_n<mode>" - [(match_operand:<V_widen> 0 "s_register_operand" "") - (match_operand:VMDI 1 "s_register_operand" "") - (match_operand:<V_elem> 2 "s_register_operand" "")] + [(match_operand:<V_widen> 0 "s_register_operand") + (match_operand:VMDI 1 "s_register_operand") + (match_operand:<V_elem> 2 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4720,9 +4720,9 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vqdmull_n<mode>" - [(match_operand:<V_widen> 0 "s_register_operand" "") - (match_operand:VMDI 1 "s_register_operand" "") - (match_operand:<V_elem> 2 "s_register_operand" "")] + [(match_operand:<V_widen> 0 "s_register_operand") + (match_operand:VMDI 1 "s_register_operand") + (match_operand:<V_elem> 2 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4733,9 +4733,9 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vqdmulh_n<mode>" - [(match_operand:VMDI 0 "s_register_operand" "") - (match_operand:VMDI 1 "s_register_operand" "") - (match_operand:<V_elem> 2 "s_register_operand" "")] + [(match_operand:VMDI 0 "s_register_operand") + (match_operand:VMDI 1 "s_register_operand") + (match_operand:<V_elem> 2 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4746,9 +4746,9 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vqrdmulh_n<mode>" - [(match_operand:VMDI 0 "s_register_operand" "") - (match_operand:VMDI 1 "s_register_operand" "") - (match_operand:<V_elem> 2 "s_register_operand" "")] + [(match_operand:VMDI 0 "s_register_operand") + (match_operand:VMDI 1 "s_register_operand") + (match_operand:<V_elem> 2 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4759,9 +4759,9 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vqdmulh_n<mode>" - [(match_operand:VMQI 0 "s_register_operand" "") - (match_operand:VMQI 1 "s_register_operand" "") - (match_operand:<V_elem> 2 "s_register_operand" "")] + [(match_operand:VMQI 0 "s_register_operand") + (match_operand:VMQI 1 "s_register_operand") + (match_operand:<V_elem> 2 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<V_HALF>mode); @@ -4772,9 +4772,9 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vqrdmulh_n<mode>" - [(match_operand:VMQI 0 "s_register_operand" "") - (match_operand:VMQI 1 "s_register_operand" "") - (match_operand:<V_elem> 2 "s_register_operand" "")] + [(match_operand:VMQI 0 "s_register_operand") + (match_operand:VMQI 1 "s_register_operand") + (match_operand:<V_elem> 2 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<V_HALF>mode); @@ -4785,10 +4785,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmla_n<mode>" - [(match_operand:VMD 0 "s_register_operand" "") - (match_operand:VMD 1 "s_register_operand" "") - (match_operand:VMD 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:VMD 0 "s_register_operand") + (match_operand:VMD 1 "s_register_operand") + (match_operand:VMD 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4799,10 +4799,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmla_n<mode>" - [(match_operand:VMQ 0 "s_register_operand" "") - (match_operand:VMQ 1 "s_register_operand" "") - (match_operand:VMQ 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:VMQ 0 "s_register_operand") + (match_operand:VMQ 1 "s_register_operand") + (match_operand:VMQ 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<V_HALF>mode); @@ -4813,10 +4813,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmlals_n<mode>" - [(match_operand:<V_widen> 0 "s_register_operand" "") - (match_operand:<V_widen> 1 "s_register_operand" "") - (match_operand:VMDI 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:<V_widen> 0 "s_register_operand") + (match_operand:<V_widen> 1 "s_register_operand") + (match_operand:VMDI 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4827,10 +4827,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmlalu_n<mode>" - [(match_operand:<V_widen> 0 "s_register_operand" "") - (match_operand:<V_widen> 1 "s_register_operand" "") - (match_operand:VMDI 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:<V_widen> 0 "s_register_operand") + (match_operand:<V_widen> 1 "s_register_operand") + (match_operand:VMDI 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4841,10 +4841,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vqdmlal_n<mode>" - [(match_operand:<V_widen> 0 "s_register_operand" "") - (match_operand:<V_widen> 1 "s_register_operand" "") - (match_operand:VMDI 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:<V_widen> 0 "s_register_operand") + (match_operand:<V_widen> 1 "s_register_operand") + (match_operand:VMDI 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4855,10 +4855,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmls_n<mode>" - [(match_operand:VMD 0 "s_register_operand" "") - (match_operand:VMD 1 "s_register_operand" "") - (match_operand:VMD 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:VMD 0 "s_register_operand") + (match_operand:VMD 1 "s_register_operand") + (match_operand:VMD 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4869,10 +4869,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmls_n<mode>" - [(match_operand:VMQ 0 "s_register_operand" "") - (match_operand:VMQ 1 "s_register_operand" "") - (match_operand:VMQ 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:VMQ 0 "s_register_operand") + (match_operand:VMQ 1 "s_register_operand") + (match_operand:VMQ 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<V_HALF>mode); @@ -4883,10 +4883,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmlsls_n<mode>" - [(match_operand:<V_widen> 0 "s_register_operand" "") - (match_operand:<V_widen> 1 "s_register_operand" "") - (match_operand:VMDI 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:<V_widen> 0 "s_register_operand") + (match_operand:<V_widen> 1 "s_register_operand") + (match_operand:VMDI 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4897,10 +4897,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vmlslu_n<mode>" - [(match_operand:<V_widen> 0 "s_register_operand" "") - (match_operand:<V_widen> 1 "s_register_operand" "") - (match_operand:VMDI 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:<V_widen> 0 "s_register_operand") + (match_operand:<V_widen> 1 "s_register_operand") + (match_operand:VMDI 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4911,10 +4911,10 @@ if (BYTES_BIG_ENDIAN) }) (define_expand "neon_vqdmlsl_n<mode>" - [(match_operand:<V_widen> 0 "s_register_operand" "") - (match_operand:<V_widen> 1 "s_register_operand" "") - (match_operand:VMDI 2 "s_register_operand" "") - (match_operand:<V_elem> 3 "s_register_operand" "")] + [(match_operand:<V_widen> 0 "s_register_operand") + (match_operand:<V_widen> 1 "s_register_operand") + (match_operand:VMDI 2 "s_register_operand") + (match_operand:<V_elem> 3 "s_register_operand")] "TARGET_NEON" { rtx tmp = gen_reg_rtx (<MODE>mode); @@ -4988,10 +4988,10 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "neon_vbsl<mode>" - [(set (match_operand:VDQX 0 "s_register_operand" "") - (unspec:VDQX [(match_operand:<V_cmp_result> 1 "s_register_operand" "") - (match_operand:VDQX 2 "s_register_operand" "") - (match_operand:VDQX 3 "s_register_operand" "")] + [(set (match_operand:VDQX 0 "s_register_operand") + (unspec:VDQX [(match_operand:<V_cmp_result> 1 "s_register_operand") + (match_operand:VDQX 2 "s_register_operand") + (match_operand:VDQX 3 "s_register_operand")] UNSPEC_VBSL))] "TARGET_NEON" { @@ -5470,7 +5470,7 @@ if (BYTES_BIG_ENDIAN) (unspec:VDQWH [(match_operand:VDQWH 1 "s_register_operand") (match_operand:VDQWH 2 "s_register_operand")] UNSPEC_VUZP1)) - (set (match_operand:VDQWH 3 "s_register_operand" "") + (set (match_operand:VDQWH 3 "s_register_operand") (unspec:VDQWH [(match_dup 1) (match_dup 2)] UNSPEC_VUZP2))])] "TARGET_NEON" "" @@ -5566,8 +5566,8 @@ if (BYTES_BIG_ENDIAN) ;; Special case for DImode. Treat it exactly like a simple load. (define_expand "neon_vld1_dupdi" - [(set (match_operand:DI 0 "s_register_operand" "") - (unspec:DI [(match_operand:DI 1 "neon_struct_operand" "")] + [(set (match_operand:DI 0 "s_register_operand") + (unspec:DI [(match_operand:DI 1 "neon_struct_operand")] UNSPEC_VLD1))] "TARGET_NEON" "" @@ -6541,7 +6541,7 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_unpack<US>_hi_<mode>" - [(match_operand:<V_unpack> 0 "register_operand" "") + [(match_operand:<V_unpack> 0 "register_operand") (SE:<V_unpack> (match_operand:VU 1 "register_operand"))] "TARGET_NEON && !BYTES_BIG_ENDIAN" { @@ -6560,8 +6560,8 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_unpack<US>_lo_<mode>" - [(match_operand:<V_unpack> 0 "register_operand" "") - (SE:<V_unpack> (match_operand:VU 1 "register_operand" ""))] + [(match_operand:<V_unpack> 0 "register_operand") + (SE:<V_unpack> (match_operand:VU 1 "register_operand"))] "TARGET_NEON && !BYTES_BIG_ENDIAN" { rtvec v = rtvec_alloc (<V_mode_nunits>/2) ; @@ -6591,9 +6591,9 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_widen_<US>mult_lo_<mode>" - [(match_operand:<V_unpack> 0 "register_operand" "") - (SE:<V_unpack> (match_operand:VU 1 "register_operand" "")) - (SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))] + [(match_operand:<V_unpack> 0 "register_operand") + (SE:<V_unpack> (match_operand:VU 1 "register_operand")) + (SE:<V_unpack> (match_operand:VU 2 "register_operand"))] "TARGET_NEON && !BYTES_BIG_ENDIAN" { rtvec v = rtvec_alloc (<V_mode_nunits>/2) ; @@ -6625,9 +6625,9 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_widen_<US>mult_hi_<mode>" - [(match_operand:<V_unpack> 0 "register_operand" "") - (SE:<V_unpack> (match_operand:VU 1 "register_operand" "")) - (SE:<V_unpack> (match_operand:VU 2 "register_operand" ""))] + [(match_operand:<V_unpack> 0 "register_operand") + (SE:<V_unpack> (match_operand:VU 1 "register_operand")) + (SE:<V_unpack> (match_operand:VU 2 "register_operand"))] "TARGET_NEON && !BYTES_BIG_ENDIAN" { rtvec v = rtvec_alloc (<V_mode_nunits>/2) ; @@ -6658,9 +6658,9 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_widen_<US>shiftl_lo_<mode>" - [(match_operand:<V_unpack> 0 "register_operand" "") - (SE:<V_unpack> (match_operand:VU 1 "register_operand" "")) - (match_operand:SI 2 "immediate_operand" "i")] + [(match_operand:<V_unpack> 0 "register_operand") + (SE:<V_unpack> (match_operand:VU 1 "register_operand")) + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON && !BYTES_BIG_ENDIAN" { emit_insn (gen_neon_vec_<US>shiftl_<V_half> (operands[0], @@ -6671,9 +6671,9 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_widen_<US>shiftl_hi_<mode>" - [(match_operand:<V_unpack> 0 "register_operand" "") - (SE:<V_unpack> (match_operand:VU 1 "register_operand" "")) - (match_operand:SI 2 "immediate_operand" "i")] + [(match_operand:<V_unpack> 0 "register_operand") + (SE:<V_unpack> (match_operand:VU 1 "register_operand")) + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON && !BYTES_BIG_ENDIAN" { emit_insn (gen_neon_vec_<US>shiftl_<V_half> (operands[0], @@ -6694,7 +6694,7 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_unpack<US>_lo_<mode>" - [(match_operand:<V_double_width> 0 "register_operand" "") + [(match_operand:<V_double_width> 0 "register_operand") (SE:<V_double_width>(match_operand:VDI 1 "register_operand"))] "TARGET_NEON" { @@ -6707,7 +6707,7 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_unpack<US>_hi_<mode>" - [(match_operand:<V_double_width> 0 "register_operand" "") + [(match_operand:<V_double_width> 0 "register_operand") (SE:<V_double_width>(match_operand:VDI 1 "register_operand"))] "TARGET_NEON" { @@ -6731,9 +6731,9 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_widen_<US>mult_hi_<mode>" - [(match_operand:<V_double_width> 0 "register_operand" "") - (SE:<V_double_width> (match_operand:VDI 1 "register_operand" "")) - (SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))] + [(match_operand:<V_double_width> 0 "register_operand") + (SE:<V_double_width> (match_operand:VDI 1 "register_operand")) + (SE:<V_double_width> (match_operand:VDI 2 "register_operand"))] "TARGET_NEON" { rtx tmpreg = gen_reg_rtx (<V_widen>mode); @@ -6746,9 +6746,9 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_widen_<US>mult_lo_<mode>" - [(match_operand:<V_double_width> 0 "register_operand" "") - (SE:<V_double_width> (match_operand:VDI 1 "register_operand" "")) - (SE:<V_double_width> (match_operand:VDI 2 "register_operand" ""))] + [(match_operand:<V_double_width> 0 "register_operand") + (SE:<V_double_width> (match_operand:VDI 1 "register_operand")) + (SE:<V_double_width> (match_operand:VDI 2 "register_operand"))] "TARGET_NEON" { rtx tmpreg = gen_reg_rtx (<V_widen>mode); @@ -6761,9 +6761,9 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_widen_<US>shiftl_hi_<mode>" - [(match_operand:<V_double_width> 0 "register_operand" "") - (SE:<V_double_width> (match_operand:VDI 1 "register_operand" "")) - (match_operand:SI 2 "immediate_operand" "i")] + [(match_operand:<V_double_width> 0 "register_operand") + (SE:<V_double_width> (match_operand:VDI 1 "register_operand")) + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { rtx tmpreg = gen_reg_rtx (<V_widen>mode); @@ -6775,9 +6775,9 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_widen_<US>shiftl_lo_<mode>" - [(match_operand:<V_double_width> 0 "register_operand" "") - (SE:<V_double_width> (match_operand:VDI 1 "register_operand" "")) - (match_operand:SI 2 "immediate_operand" "i")] + [(match_operand:<V_double_width> 0 "register_operand") + (SE:<V_double_width> (match_operand:VDI 1 "register_operand")) + (match_operand:SI 2 "immediate_operand")] "TARGET_NEON" { rtx tmpreg = gen_reg_rtx (<V_widen>mode); @@ -6815,8 +6815,8 @@ if (BYTES_BIG_ENDIAN) ) (define_expand "vec_pack_trunc_<mode>" - [(match_operand:<V_narrow_pack> 0 "register_operand" "") - (match_operand:VSHFT 1 "register_operand" "") + [(match_operand:<V_narrow_pack> 0 "register_operand") + (match_operand:VSHFT 1 "register_operand") (match_operand:VSHFT 2 "register_operand")] "TARGET_NEON && !BYTES_BIG_ENDIAN" { diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index 0e777a9..3d49aef 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -170,11 +170,11 @@ }) (define_expand "atomic_compare_and_swap<mode>" - [(match_operand:SI 0 "s_register_operand" "") ;; bool out - (match_operand:QHSD 1 "s_register_operand" "") ;; val out - (match_operand:QHSD 2 "mem_noofs_operand" "") ;; memory - (match_operand:QHSD 3 "general_operand" "") ;; expected - (match_operand:QHSD 4 "s_register_operand" "") ;; desired + [(match_operand:SI 0 "s_register_operand") ;; bool out + (match_operand:QHSD 1 "s_register_operand") ;; val out + (match_operand:QHSD 2 "mem_noofs_operand") ;; memory + (match_operand:QHSD 3 "general_operand") ;; expected + (match_operand:QHSD 4 "s_register_operand") ;; desired (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index b199349..b142bfc 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -794,9 +794,9 @@ (set_attr "conds" "clob,nocond,nocond,nocond,nocond,clob,nocond")]) (define_expand "thumb_movhi_clobber" - [(set (match_operand:HI 0 "memory_operand" "") - (match_operand:HI 1 "register_operand" "")) - (clobber (match_operand:DI 2 "register_operand" ""))] + [(set (match_operand:HI 0 "memory_operand") + (match_operand:HI 1 "register_operand")) + (clobber (match_operand:DI 2 "register_operand"))] "TARGET_THUMB1" " if (strict_memory_address_p (HImode, XEXP (operands[0], 0)) @@ -977,8 +977,8 @@ (define_expand "cbranchqi4" [(set (pc) (if_then_else (match_operator 0 "lt_ge_comparison_operator" - [(match_operand:QI 1 "memory_operand" "") - (match_operand:QI 2 "const0_operand" "")]) + [(match_operand:QI 1 "memory_operand") + (match_operand:QI 2 "const0_operand")]) (label_ref (match_operand 3 "" "")) (pc)))] "TARGET_THUMB1" @@ -1616,8 +1616,8 @@ (define_expand "cstoresi_eq0_thumb1" [(parallel - [(set (match_operand:SI 0 "s_register_operand" "") - (eq:SI (match_operand:SI 1 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand") + (eq:SI (match_operand:SI 1 "s_register_operand") (const_int 0))) (clobber (match_dup:SI 2))])] "TARGET_THUMB1" @@ -1626,8 +1626,8 @@ (define_expand "cstoresi_ne0_thumb1" [(parallel - [(set (match_operand:SI 0 "s_register_operand" "") - (ne:SI (match_operand:SI 1 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand") + (ne:SI (match_operand:SI 1 "s_register_operand") (const_int 0))) (clobber (match_dup:SI 2))])] "TARGET_THUMB1" @@ -1838,8 +1838,8 @@ ) (define_expand "thumb1_casesi_internal_pic" - [(match_operand:SI 0 "s_register_operand" "") - (match_operand:SI 1 "thumb1_cmp_operand" "") + [(match_operand:SI 0 "s_register_operand") + (match_operand:SI 1 "thumb1_cmp_operand") (match_operand 2 "" "") (match_operand 3 "" "")] "TARGET_THUMB1" @@ -1911,7 +1911,7 @@ ;; Miscellaneous Thumb patterns (define_expand "tablejump" - [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "")) + [(parallel [(set (pc) (match_operand:SI 0 "register_operand")) (use (label_ref (match_operand 1 "" "")))])] "TARGET_THUMB1" " diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index bb7883f..99a430e 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -21,8 +21,8 @@ ;; Vector Moves (define_expand "mov<mode>" - [(set (match_operand:VALL 0 "nonimmediate_operand" "") - (match_operand:VALL 1 "general_operand" ""))] + [(set (match_operand:VALL 0 "nonimmediate_operand") + (match_operand:VALL 1 "general_operand"))] "TARGET_NEON || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" { @@ -42,9 +42,9 @@ ;; patterns separately for IWMMXT and Neon. (define_expand "add<mode>3" - [(set (match_operand:VALL 0 "s_register_operand" "") - (plus:VALL (match_operand:VALL 1 "s_register_operand" "") - (match_operand:VALL 2 "s_register_operand" "")))] + [(set (match_operand:VALL 0 "s_register_operand") + (plus:VALL (match_operand:VALL 1 "s_register_operand") + (match_operand:VALL 2 "s_register_operand")))] "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) || flag_unsafe_math_optimizations)) || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" @@ -52,9 +52,9 @@ }) (define_expand "sub<mode>3" - [(set (match_operand:VALL 0 "s_register_operand" "") - (minus:VALL (match_operand:VALL 1 "s_register_operand" "") - (match_operand:VALL 2 "s_register_operand" "")))] + [(set (match_operand:VALL 0 "s_register_operand") + (minus:VALL (match_operand:VALL 1 "s_register_operand") + (match_operand:VALL 2 "s_register_operand")))] "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) || flag_unsafe_math_optimizations)) || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" @@ -62,9 +62,9 @@ }) (define_expand "mul<mode>3" - [(set (match_operand:VALLW 0 "s_register_operand" "") - (mult:VALLW (match_operand:VALLW 1 "s_register_operand" "") - (match_operand:VALLW 2 "s_register_operand" "")))] + [(set (match_operand:VALLW 0 "s_register_operand") + (mult:VALLW (match_operand:VALLW 1 "s_register_operand") + (match_operand:VALLW 2 "s_register_operand")))] "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) || flag_unsafe_math_optimizations)) || (<MODE>mode == V4HImode && TARGET_REALLY_IWMMXT)" @@ -72,9 +72,9 @@ }) (define_expand "smin<mode>3" - [(set (match_operand:VALLW 0 "s_register_operand" "") - (smin:VALLW (match_operand:VALLW 1 "s_register_operand" "") - (match_operand:VALLW 2 "s_register_operand" "")))] + [(set (match_operand:VALLW 0 "s_register_operand") + (smin:VALLW (match_operand:VALLW 1 "s_register_operand") + (match_operand:VALLW 2 "s_register_operand")))] "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) || flag_unsafe_math_optimizations)) || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" @@ -82,18 +82,18 @@ }) (define_expand "umin<mode>3" - [(set (match_operand:VINTW 0 "s_register_operand" "") - (umin:VINTW (match_operand:VINTW 1 "s_register_operand" "") - (match_operand:VINTW 2 "s_register_operand" "")))] + [(set (match_operand:VINTW 0 "s_register_operand") + (umin:VINTW (match_operand:VINTW 1 "s_register_operand") + (match_operand:VINTW 2 "s_register_operand")))] "TARGET_NEON || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" { }) (define_expand "smax<mode>3" - [(set (match_operand:VALLW 0 "s_register_operand" "") - (smax:VALLW (match_operand:VALLW 1 "s_register_operand" "") - (match_operand:VALLW 2 "s_register_operand" "")))] + [(set (match_operand:VALLW 0 "s_register_operand") + (smax:VALLW (match_operand:VALLW 1 "s_register_operand") + (match_operand:VALLW 2 "s_register_operand")))] "(TARGET_NEON && ((<MODE>mode != V2SFmode && <MODE>mode != V4SFmode) || flag_unsafe_math_optimizations)) || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" @@ -101,19 +101,19 @@ }) (define_expand "umax<mode>3" - [(set (match_operand:VINTW 0 "s_register_operand" "") - (umax:VINTW (match_operand:VINTW 1 "s_register_operand" "") - (match_operand:VINTW 2 "s_register_operand" "")))] + [(set (match_operand:VINTW 0 "s_register_operand") + (umax:VINTW (match_operand:VINTW 1 "s_register_operand") + (match_operand:VINTW 2 "s_register_operand")))] "TARGET_NEON || (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))" { }) (define_expand "vec_perm<mode>" - [(match_operand:VE 0 "s_register_operand" "") - (match_operand:VE 1 "s_register_operand" "") - (match_operand:VE 2 "s_register_operand" "") - (match_operand:VE 3 "s_register_operand" "")] + [(match_operand:VE 0 "s_register_operand") + (match_operand:VE 1 "s_register_operand") + (match_operand:VE 2 "s_register_operand") + (match_operand:VE 3 "s_register_operand")] "TARGET_NEON && !BYTES_BIG_ENDIAN" { arm_expand_vec_perm (operands[0], operands[1], operands[2], operands[3]); |