diff options
| author | Mihailo Stojanovic <mistojanovic@wavecomp.com> | 2019-08-23 19:04:56 +0000 |
|---|---|---|
| committer | Jeff Law <law@gcc.gnu.org> | 2019-08-23 13:04:56 -0600 |
| commit | 7d35d2bf5a15e38122083ddd198d1d20548d0ffa (patch) | |
| tree | a791bda7b57d26dfef3bede54bb49017aab97fd2 | |
| parent | 0448240b88ceb5bb29d4872f434ddf385a30f1d2 (diff) | |
| download | gcc-7d35d2bf5a15e38122083ddd198d1d20548d0ffa.zip gcc-7d35d2bf5a15e38122083ddd198d1d20548d0ffa.tar.gz gcc-7d35d2bf5a15e38122083ddd198d1d20548d0ffa.tar.bz2 | |
mips.md (mips_get_fcsr, [...]): Use SI machine mode for unspec_volatile operand.
* config/mips/mips.md (mips_get_fcsr, *mips_get_fcsr): Use SI
machine mode for unspec_volatile operand.
* gcc.target/mips/get-fcsr-3.c: New test.
From-SVN: r274863
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/get-fcsr-3.c | 9 |
4 files changed, 20 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3fbdb93..989dff7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-08-23 Mihailo Stojanovic <mistojanovic@wavecomp.com> + + * config/mips/mips.md (mips_get_fcsr, *mips_get_fcsr): Use SI + machine mode for unspec_volatile operand. + 2019-08-23 Wilco Dijkstra <wdijkstr@arm.com> * gcc/doc/invoke.texi (mneon-for-64bits): Deprecate option. diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index e17b1d5..4ad5c62 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7588,7 +7588,7 @@ ;; __builtin_mips_get_fcsr: move the FCSR into operand 0. (define_expand "mips_get_fcsr" [(set (match_operand:SI 0 "register_operand") - (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))] + (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] "TARGET_HARD_FLOAT_ABI" { if (TARGET_MIPS16) @@ -7600,7 +7600,7 @@ (define_insn "*mips_get_fcsr" [(set (match_operand:SI 0 "register_operand" "=d") - (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))] + (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] "TARGET_HARD_FLOAT" "cfc1\t%0,$31") diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 887496e..92e6da2 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-08-23 Mihailo Stojanovic <mistojanovic@wavecomp.com> + + * gcc.target/mips/get-fcsr-3.c: New test. + 2019-08-23 Martin Sebor <msebor@redhat.com> * gcc.dg/Warray-bounds-36.c: Make functions static to avoid failures diff --git a/gcc/testsuite/gcc.target/mips/get-fcsr-3.c b/gcc/testsuite/gcc.target/mips/get-fcsr-3.c new file mode 100644 index 0000000..7bb97b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/get-fcsr-3.c @@ -0,0 +1,9 @@ +/* { dg-options "-mabi=64 -mhard-float" } */ + +NOMIPS16 unsigned int +foo (void) +{ + return __builtin_mips_get_fcsr () & 0x1; +} + +/* { dg-final { scan-assembler "cfc1" } } */ |