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| author | Kazu Hirata <kazu@cs.umass.edu> | 2003-02-19 21:21:21 +0000 |
|---|---|---|
| committer | Kazu Hirata <kazu@gcc.gnu.org> | 2003-02-19 21:21:21 +0000 |
| commit | 472f272337752547c77fc9607f627edb08afcd61 (patch) | |
| tree | bcad4f4791fc9fb3267ab4da028df814fced5a6f | |
| parent | 6d9cc15b64b2a3f2520f73df963fae2c1ea34abe (diff) | |
| download | gcc-472f272337752547c77fc9607f627edb08afcd61.zip gcc-472f272337752547c77fc9607f627edb08afcd61.tar.gz gcc-472f272337752547c77fc9607f627edb08afcd61.tar.bz2 | |
h8300.c (output_logical_op): Optimize or.l when ORing with 0xffff??00 with the highest bit of the ?? part set.
* config/h8300/h8300.c (output_logical_op): Optimize or.l when
ORing with 0xffff??00 with the highest bit of the ?? part set.
(compute_logical_op_length): Update.
(compute_logical_op_cc): Likewise.
From-SVN: r63131
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/h8300/h8300.c | 36 |
2 files changed, 40 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index d083a31..fb7d442 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2003-02-19 Kazu Hirata <kazu@cs.umass.edu> + + * config/h8300/h8300.c (output_logical_op): Optimize or.l when + ORing with 0xffff??00 with the highest bit of the ?? part set. + (compute_logical_op_length): Update. + (compute_logical_op_cc): Likewise. + 2003-02-19 Josef Zlomek <zlomekj@suse.cz> * bb-reorder.c (find_traces_1_round): Fixed condition for small diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c index 173946c..08a7cc6 100644 --- a/gcc/config/h8300/h8300.c +++ b/gcc/config/h8300/h8300.c @@ -2206,7 +2206,9 @@ output_logical_op (mode, operands) using multiple insns. */ if ((TARGET_H8300H || TARGET_H8300S) && w0 != 0 && w1 != 0 - && !(lower_half_easy_p && upper_half_easy_p)) + && !(lower_half_easy_p && upper_half_easy_p) + && !(code == IOR && w1 == 0xffff + && (w0 & 0x8000) != 0 && lower_half_easy_p)) { sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname); output_asm_insn (insn_buf, operands); @@ -2251,6 +2253,13 @@ output_logical_op (mode, operands) ? "sub.w\t%e0,%e0" : "not.w\t%e0", operands); else if ((TARGET_H8300H || TARGET_H8300S) + && code == IOR + && w1 == 0xffff + && (w0 & 0x8000) != 0) + { + output_asm_insn ("exts.l\t%S0", operands); + } + else if ((TARGET_H8300H || TARGET_H8300S) && code == AND && w1 == 0xff00) { @@ -2354,7 +2363,9 @@ compute_logical_op_length (mode, operands) using multiple insns. */ if ((TARGET_H8300H || TARGET_H8300S) && w0 != 0 && w1 != 0 - && !(lower_half_easy_p && upper_half_easy_p)) + && !(lower_half_easy_p && upper_half_easy_p) + && !(code == IOR && w1 == 0xffff + && (w0 & 0x8000) != 0 && lower_half_easy_p)) { if (REG_P (operands[2])) length += 4; @@ -2395,6 +2406,13 @@ compute_logical_op_length (mode, operands) length += 2; } else if ((TARGET_H8300H || TARGET_H8300S) + && code == IOR + && w1 == 0xffff + && (w0 & 0x8000) != 0) + { + length += 2; + } + else if ((TARGET_H8300H || TARGET_H8300S) && code == AND && w1 == 0xff00) { @@ -2475,10 +2493,22 @@ compute_logical_op_cc (mode, operands) using multiple insns. */ if ((TARGET_H8300H || TARGET_H8300S) && w0 != 0 && w1 != 0 - && !(lower_half_easy_p && upper_half_easy_p)) + && !(lower_half_easy_p && upper_half_easy_p) + && !(code == IOR && w1 == 0xffff + && (w0 & 0x8000) != 0 && lower_half_easy_p)) { cc = CC_SET_ZNV; } + else + { + if ((TARGET_H8300H || TARGET_H8300S) + && code == IOR + && w1 == 0xffff + && (w0 & 0x8000) != 0) + { + cc = CC_SET_ZNV; + } + } break; default: abort (); |