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| author | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | 2009-08-24 09:03:35 +0000 |
|---|---|---|
| committer | Ramana Radhakrishnan <ramana@gcc.gnu.org> | 2009-08-24 09:03:35 +0000 |
| commit | 3e2d9dcfa8d8a0bbb136b569e91a2c0687c930c7 (patch) | |
| tree | 8ae627b9aadc4ebbe7fd0082ea16a0de542345e7 | |
| parent | 54f52b81641ce93ebb60a8d62f09ece24b1fa946 (diff) | |
| download | gcc-3e2d9dcfa8d8a0bbb136b569e91a2c0687c930c7.zip gcc-3e2d9dcfa8d8a0bbb136b569e91a2c0687c930c7.tar.gz gcc-3e2d9dcfa8d8a0bbb136b569e91a2c0687c930c7.tar.bz2 | |
combine cmps with shifts
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* gcc.target/arm/combine-cmp-shift.c: New test.
2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm.c (arm_select_cc_mode): Handle subreg.
From-SVN: r151050
| -rw-r--r-- | gcc/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/combine-cmp-shift.c | 15 |
4 files changed, 27 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f415575..fc6fa1e 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,9 @@ 2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + * config/arm/arm.c (arm_select_cc_mode): Handle subreg. + +2009-08-24 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + * config/arm/vfp.md (*arm_movdi_vfp): Mark as predicable. (*arm_movdf_vfp): Likewise. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 3c7e67e..0d53896 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -9504,7 +9504,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) /* A compare with a shifted operand. Because of canonicalization, the comparison will have to be swapped when we emit the assembler. */ - if (GET_MODE (y) == SImode && GET_CODE (y) == REG + if (GET_MODE (y) == SImode + && (REG_P (y) || (GET_CODE (y) == SUBREG)) && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE || GET_CODE (x) == ROTATERT)) @@ -9512,7 +9513,8 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) /* This operation is performed swapped, but since we only rely on the Z flag we don't need an additional mode. */ - if (GET_MODE (y) == SImode && REG_P (y) + if (GET_MODE (y) == SImode + && (REG_P (y) || (GET_CODE (y) == SUBREG)) && GET_CODE (x) == NEG && (op == EQ || op == NE)) return CC_Zmode; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 896c681..3716a90 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2009-08-11 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> + + * gcc.target/arm/combine-cmp-shift.c: New test. + 2009-08-24 Kai Tietz <kai.tietz@onevision.com> *gcc.dg/format/ms-format1.c: Add new cases for I32 diff --git a/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c b/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c new file mode 100644 index 0000000..1cacc29 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/combine-cmp-shift.c @@ -0,0 +1,15 @@ +/* { dg-options "-O2 -mcpu=cortex-a8" } */ +/* { dg-final { scan-assembler "cmp\tr\[0-9\]*, r\[0-9\]*, asr #31" } } */ + +typedef int SItype __attribute__ ((mode (SI))); +typedef int DItype __attribute__ ((mode (DI))); +void abort (void); + +SItype +__mulvsi3 (SItype a, SItype b) +{ + const DItype w = (DItype) a * (DItype) b; + if ((SItype) (w >> (4 * 8)) != (SItype) w >> ((4 * 8) - 1)) + abort (); + return w; +} |