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| author | Jeff Law <law@redhat.com> | 2017-04-13 23:13:19 -0600 |
|---|---|---|
| committer | Jeff Law <law@gcc.gnu.org> | 2017-04-13 23:13:19 -0600 |
| commit | 1f33abd75db99567376f41a9f21cbf509167aa97 (patch) | |
| tree | b2dfa0fbd477405ed49c014a9c3f83cd45308f6c | |
| parent | 67630cef4dca6266d75837939c6d87b6a6d23bf8 (diff) | |
| download | gcc-1f33abd75db99567376f41a9f21cbf509167aa97.zip gcc-1f33abd75db99567376f41a9f21cbf509167aa97.tar.gz gcc-1f33abd75db99567376f41a9f21cbf509167aa97.tar.bz2 | |
mips.mips.md (zero_extendsidi2): Do not allow SP to appear in operands[1] if it is a MEM and TARGET_MIPS16 is active.
* config/mips.mips.md (zero_extendsidi2): Do not allow SP to appear
in operands[1] if it is a MEM and TARGET_MIPS16 is active.
(zero_extendsidi2_dext): Likewise.
From-SVN: r246924
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 10 |
2 files changed, 14 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 33b094e..788f029 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2017-04-13 Jeff Law <law@redhat.com> + + * config/mips.mips.md (zero_extendsidi2): Do not allow SP to appear + in operands[1] if it is a MEM and TARGET_MIPS16 is active. + (zero_extendsidi2_dext): Likewise. + 2017-04-13 Jakub Jelinek <jakub@redhat.com> PR sanitizer/80403 diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 7acf00d..dd5e1e7 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3493,7 +3493,10 @@ (define_insn_and_split "*zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=d,d") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] - "TARGET_64BIT && !ISA_HAS_EXT_INS" + "TARGET_64BIT && !ISA_HAS_EXT_INS + && !(TARGET_MIPS16 + && MEM_P (operands[1]) + && reg_mentioned_p (stack_pointer_rtx, operands[1]))" "@ # lwu\t%0,%1" @@ -3509,7 +3512,10 @@ (define_insn "*zero_extendsidi2_dext" [(set (match_operand:DI 0 "register_operand" "=d,d") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))] - "TARGET_64BIT && ISA_HAS_EXT_INS" + "TARGET_64BIT && ISA_HAS_EXT_INS + && !(TARGET_MIPS16 + && MEM_P (operands[1]) + && reg_mentioned_p (stack_pointer_rtx, operands[1]))" "@ dext\t%0,%1,0,32 lwu\t%0,%1" |