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| author | Renlin Li <renlin.li@arm.com> | 2015-10-09 16:22:33 +0000 |
|---|---|---|
| committer | Renlin Li <renlin@gcc.gnu.org> | 2015-10-09 16:22:33 +0000 |
| commit | 97400916d7e9f621e37ee1c09d30335b95c453ab (patch) | |
| tree | c95d9178cd9f568b78d15d7275c62a0b8527b479 | |
| parent | 84ff66b884e9a67d83fa58c659a3aff52b38e138 (diff) | |
| download | gcc-97400916d7e9f621e37ee1c09d30335b95c453ab.zip gcc-97400916d7e9f621e37ee1c09d30335b95c453ab.tar.gz gcc-97400916d7e9f621e37ee1c09d30335b95c453ab.tar.bz2 | |
[PATCH][ARM]Add earlyclobber modifier for neon_(vtrn, vuzp, vzip)<mode>_insn rtx
pattern.
gcc/
2015-10-09 Renlin Li <renlin.li@arm.com>
* config/arm/neon.md (neon_vuzp<mode>_insn): Add & modifier for
operands[0] and operands[2].
(neon_vtrn<mode>_insn): Likewise.
(neon_vzip<mode>_insn): Likewise.
From-SVN: r228662
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/neon.md | 12 |
2 files changed, 13 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 6156bd0..932253d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2015-10-09 Renlin Li <renlin.li@arm.com> + + * config/arm/neon.md (neon_vuzp<mode>_insn): Add & modifier for + operands[0] and operands[2]. + (neon_vtrn<mode>_insn): Likewise. + (neon_vzip<mode>_insn): Likewise. + 2015-10-09 Andre Vieira <andre.simoesdiasvieira@arm.com> * match.pd: ((X inner_op C0) outer_op C1) New pattern. diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 2667866..e5a2b0f 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -4074,11 +4074,11 @@ if (BYTES_BIG_ENDIAN) ;; Note: Different operand numbering to handle tied registers correctly. (define_insn "*neon_vtrn<mode>_insn" - [(set (match_operand:VDQW 0 "s_register_operand" "=w") + [(set (match_operand:VDQW 0 "s_register_operand" "=&w") (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") (match_operand:VDQW 3 "s_register_operand" "2")] UNSPEC_VTRN1)) - (set (match_operand:VDQW 2 "s_register_operand" "=w") + (set (match_operand:VDQW 2 "s_register_operand" "=&w") (unspec:VDQW [(match_dup 1) (match_dup 3)] UNSPEC_VTRN2))] "TARGET_NEON" @@ -4100,11 +4100,11 @@ if (BYTES_BIG_ENDIAN) ;; Note: Different operand numbering to handle tied registers correctly. (define_insn "*neon_vzip<mode>_insn" - [(set (match_operand:VDQW 0 "s_register_operand" "=w") + [(set (match_operand:VDQW 0 "s_register_operand" "=&w") (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") (match_operand:VDQW 3 "s_register_operand" "2")] UNSPEC_VZIP1)) - (set (match_operand:VDQW 2 "s_register_operand" "=w") + (set (match_operand:VDQW 2 "s_register_operand" "=&w") (unspec:VDQW [(match_dup 1) (match_dup 3)] UNSPEC_VZIP2))] "TARGET_NEON" @@ -4126,11 +4126,11 @@ if (BYTES_BIG_ENDIAN) ;; Note: Different operand numbering to handle tied registers correctly. (define_insn "*neon_vuzp<mode>_insn" - [(set (match_operand:VDQW 0 "s_register_operand" "=w") + [(set (match_operand:VDQW 0 "s_register_operand" "=&w") (unspec:VDQW [(match_operand:VDQW 1 "s_register_operand" "0") (match_operand:VDQW 3 "s_register_operand" "2")] UNSPEC_VUZP1)) - (set (match_operand:VDQW 2 "s_register_operand" "=w") + (set (match_operand:VDQW 2 "s_register_operand" "=&w") (unspec:VDQW [(match_dup 1) (match_dup 3)] UNSPEC_VUZP2))] "TARGET_NEON" |