diff options
| author | Mihailo Stojanovic <mistojanovic@wavecomp.com> | 2019-10-28 19:03:38 +0000 |
|---|---|---|
| committer | Jeff Law <law@gcc.gnu.org> | 2019-10-28 13:03:38 -0600 |
| commit | 18e2ca55d452f95bbd3739f86bad2490726ee378 (patch) | |
| tree | 183a642d6b2aab76cd9d123fa9ca5e119f0202a4 | |
| parent | e18a6d1441cfb5d43d3193a2643207fc3f95fd5a (diff) | |
| download | gcc-18e2ca55d452f95bbd3739f86bad2490726ee378.zip gcc-18e2ca55d452f95bbd3739f86bad2490726ee378.tar.gz gcc-18e2ca55d452f95bbd3739f86bad2490726ee378.tar.bz2 | |
mips-msa.md (msa_insert_<msaftm_f>): Add an alternative which covers the floating-point input value.
* config/mips/mips-msa.md (msa_insert_<msaftm_f>): Add an
alternative which covers the floating-point input value. Also
forbid the split of insert.d pattern for floating-point values.
* gcc.target/mips/msa-insert-split.c: New test.
From-SVN: r277533
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/mips/mips-msa.md | 11 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/mips/msa-insert-split.c | 16 |
4 files changed, 34 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b875cef..a3fbadf 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2019-10-28 Mihailo Stojanovic <mistojanovic@wavecomp.com> + + * config/mips/mips-msa.md (msa_insert_<msaftm_f>): Add an + alternative which covers the floating-point input value. Also + forbid the split of insert.d pattern for floating-point values. + 2019-10-28 Andrew Burgess <andrew.burgess@embecosm.com> * config.gcc: Add riscv-sr.o to extra_objs for riscv. diff --git a/gcc/config/mips/mips-msa.md b/gcc/config/mips/mips-msa.md index 929646d..628423d 100644 --- a/gcc/config/mips/mips-msa.md +++ b/gcc/config/mips/mips-msa.md @@ -436,14 +436,17 @@ }) (define_insn "msa_insert_<msafmt_f>" - [(set (match_operand:MSA 0 "register_operand" "=f") + [(set (match_operand:MSA 0 "register_operand" "=f,f") (vec_merge:MSA (vec_duplicate:MSA - (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ")) - (match_operand:MSA 2 "register_operand" "0") + (match_operand:<UNITMODE> 1 "reg_or_0_operand" "dJ,f")) + (match_operand:MSA 2 "register_operand" "0,0") (match_operand 3 "const_<bitmask>_operand" "")))] "ISA_HAS_MSA" { + if (which_alternative == 1) + return "insve.<msafmt>\t%w0[%y3],%w1[0]"; + if (!TARGET_64BIT && (<MODE>mode == V2DImode || <MODE>mode == V2DFmode)) return "#"; else @@ -462,6 +465,8 @@ "reload_completed && ISA_HAS_MSA && !TARGET_64BIT" [(const_int 0)] { + if (REG_P (operands[1]) && FP_REG_P (REGNO (operands[1]))) + FAIL; mips_split_msa_insert_d (operands[0], operands[2], operands[3], operands[1]); DONE; }) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 14b3147..e5cecf4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-10-28 Mihailo Stojanovic <mistojanovic@wavecomp.com> + + * gcc.target/mips/msa-insert-split.c: New test. + 2019-10-28 Andrew Burgess <andrew.burgess@embecosm.com> * gcc.target/riscv/save-restore-2.c: New file. diff --git a/gcc/testsuite/gcc.target/mips/msa-insert-split.c b/gcc/testsuite/gcc.target/mips/msa-insert-split.c new file mode 100644 index 0000000..50f3b8a --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/msa-insert-split.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-mfp64 -mhard-float -mmsa" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +typedef double v2f64 __attribute__ ((vector_size (16))); + +void foo (double* arr, v2f64* vec) +{ + v2f64 v; + v[0] = arr[0]; + v[1] = arr[1]; + *vec = v; +} + +/* { dg-final { scan-assembler-not "insert.w" } } */ +/* { dg-final { scan-assembler-times "insve.d" 2 } } */ |