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| author | Xianmiao Qu <cooper.qu@linux.alibaba.com> | 2024-09-01 22:28:13 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-09-01 22:28:38 -0600 |
| commit | eca320bfe340be2222ec9267bdb6021c7b387111 (patch) | |
| tree | e77a1dea75c67484583737ae7c45dc76f15223ba | |
| parent | 0562976d62e095f3a00c799288dee4e5b20114e2 (diff) | |
| download | gcc-eca320bfe340be2222ec9267bdb6021c7b387111.zip gcc-eca320bfe340be2222ec9267bdb6021c7b387111.tar.gz gcc-eca320bfe340be2222ec9267bdb6021c7b387111.tar.bz2 | |
[PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.
Currently, in RV32, even with the D extension enabled, the cost of DFmode
register moves is still set to 'COSTS_N_INSNS (2)'. This results in the
'lower-subreg' pass splitting DFmode register moves into two SImode SUBREG
register moves, leading to the generation of many redundant instructions.
As an example, consider the following test case:
double foo (int t, double a, double b)
{
if (t > 0)
return a;
else
return b;
}
When compiling with -march=rv32imafdc -mabi=ilp32d, the following code is generated:
.cfi_startproc
addi sp,sp,-32
.cfi_def_cfa_offset 32
fsd fa0,8(sp)
fsd fa1,16(sp)
lw a4,8(sp)
lw a5,12(sp)
lw a2,16(sp)
lw a3,20(sp)
bgt a0,zero,.L1
mv a4,a2
mv a5,a3
.L1:
sw a4,24(sp)
sw a5,28(sp)
fld fa0,24(sp)
addi sp,sp,32
.cfi_def_cfa_offset 0
jr ra
.cfi_endproc
After adjust the DFmode register move's cost to 'COSTS_N_INSNS (1)', the
generated code is as follows, with a significant reduction in the number
of instructions.
.cfi_startproc
ble a0,zero,.L5
ret
.L5:
fmv.d fa0,fa1
ret
.cfi_endproc
gcc/
* config/riscv/riscv.cc (riscv_rtx_costs): Optimize the cost of the
DFmode register move for RV32.
gcc/testsuite/
* gcc.target/riscv/rv32-movdf-cost.c: New test.
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rv32-movdf-cost.c | 13 |
2 files changed, 18 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 75b37b5..d03e51f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3601,6 +3601,11 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN if (outer_code == INSN && register_operand (SET_DEST (x), GET_MODE (SET_DEST (x)))) { + if (REG_P (SET_SRC (x)) && TARGET_DOUBLE_FLOAT && mode == DFmode) + { + *total = COSTS_N_INSNS (1); + return true; + } riscv_rtx_costs (SET_SRC (x), mode, outer_code, opno, total, speed); return true; } diff --git a/gcc/testsuite/gcc.target/riscv/rv32-movdf-cost.c b/gcc/testsuite/gcc.target/riscv/rv32-movdf-cost.c new file mode 100644 index 0000000..cb679e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rv32-movdf-cost.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32imafdc -mabi=ilp32d" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +double foo (int t, double a, double b) +{ + if (t > 0) + return a; + else + return b; +} + +/* { dg-final { scan-assembler-not "fsd\t" } } */ |