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| author | Levy Hsu <admin@levyhsu.com> | 2024-09-02 10:24:48 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2024-09-02 10:24:48 +0800 |
| commit | e19f65b0be1e91ff86689feb7695080dad4c9197 (patch) | |
| tree | bbe4b877156d003d18e30f621ad42466ef15af74 | |
| parent | 29ef601973d7b79338694e59581d4c24bcd07f69 (diff) | |
| download | gcc-e19f65b0be1e91ff86689feb7695080dad4c9197.zip gcc-e19f65b0be1e91ff86689feb7695080dad4c9197.tar.gz gcc-e19f65b0be1e91ff86689feb7695080dad4c9197.tar.bz2 | |
i386: Support vectorized BF16 sqrt with AVX10.2 instruction
gcc/ChangeLog:
* config/i386/sse.md: Expand VF2H to VF2HB with VBF modes.
| -rw-r--r-- | gcc/config/i386/sse.md | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b374783..2de592a 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -447,9 +447,12 @@ (define_mode_iterator VF2_AVX10_2 [(V8DF "TARGET_AVX10_2_512") V4DF V2DF]) -;; All DFmode & HFmode vector float modes -(define_mode_iterator VF2H - [(V32HF "TARGET_AVX512FP16 && TARGET_EVEX512") +;; All DFmode & HFmode & BFmode vector float modes +(define_mode_iterator VF2HB + [(V32BF "TARGET_AVX10_2_512") + (V16BF "TARGET_AVX10_2_256") + (V8BF "TARGET_AVX10_2_256") + (V32HF "TARGET_AVX512FP16 && TARGET_EVEX512") (V16HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V8HF "TARGET_AVX512FP16 && TARGET_AVX512VL") (V8DF "TARGET_AVX512F && TARGET_EVEX512") (V4DF "TARGET_AVX") V2DF]) @@ -2933,8 +2936,8 @@ (set_attr "mode" "<MODE>")]) (define_expand "sqrt<mode>2" - [(set (match_operand:VF2H 0 "register_operand") - (sqrt:VF2H (match_operand:VF2H 1 "vector_operand")))] + [(set (match_operand:VF2HB 0 "register_operand") + (sqrt:VF2HB (match_operand:VF2HB 1 "vector_operand")))] "TARGET_SSE2") (define_expand "sqrt<mode>2" |