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| author | Alexandre Oliva <oliva@adacore.com> | 2024-07-12 05:42:07 -0300 |
|---|---|---|
| committer | Alexandre Oliva <oliva@gnu.org> | 2024-07-12 05:42:07 -0300 |
| commit | ccfe7151803956d178947d0afda0bd66ce097275 (patch) | |
| tree | 2ac3453d9f6ee64ce3b37e9ab72ff849b8d3d760 | |
| parent | c6f38e5e6d900b8ed6a4f5c126d3197946cad4dd (diff) | |
| download | gcc-ccfe7151803956d178947d0afda0bd66ce097275.zip gcc-ccfe7151803956d178947d0afda0bd66ce097275.tar.gz gcc-ccfe7151803956d178947d0afda0bd66ce097275.tar.bz2 | |
[alpha] adjust MEM alignment for block move [PR115459]
Before issuing loads or stores for a block move, adjust the MEM
alignments if analysis of the addresses enabled the inference of
stricter alignment. This ensures that the MEMs are sufficiently
aligned for the corresponding insns, which avoids trouble in case of
e.g. substitutions into SUBREGs.
for gcc/ChangeLog
PR target/115459
* config/alpha/alpha.cc (alpha_expand_block_move): Adjust
MEMs to match inferred alignment.
| -rw-r--r-- | gcc/config/alpha/alpha.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/config/alpha/alpha.cc b/gcc/config/alpha/alpha.cc index a6fe95e..74631a4 100644 --- a/gcc/config/alpha/alpha.cc +++ b/gcc/config/alpha/alpha.cc @@ -3820,6 +3820,12 @@ alpha_expand_block_move (rtx operands[]) else if (a >= 16 && c % 2 == 0) src_align = 16; } + + if (MEM_P (orig_src) && MEM_ALIGN (orig_src) < src_align) + { + orig_src = shallow_copy_rtx (orig_src); + set_mem_align (orig_src, src_align); + } } tmp = XEXP (orig_dst, 0); @@ -3841,6 +3847,12 @@ alpha_expand_block_move (rtx operands[]) else if (a >= 16 && c % 2 == 0) dst_align = 16; } + + if (MEM_P (orig_dst) && MEM_ALIGN (orig_dst) < dst_align) + { + orig_dst = shallow_copy_rtx (orig_dst); + set_mem_align (orig_dst, dst_align); + } } ofs = 0; |