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| author | Yanzhang Wang <yanzhang.wang@intel.com> | 2023-08-16 22:28:50 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-08-16 22:30:00 -0600 |
| commit | e7a36e4715c7162ccfd7cd32da985d629bbd9c61 (patch) | |
| tree | c58b0bff10ddce793312edd316bce8938001b3ef | |
| parent | a32de58c9e6394e4e6aef0ac95b52d1c774ac8bc (diff) | |
| download | gcc-e7a36e4715c7162ccfd7cd32da985d629bbd9c61.zip gcc-e7a36e4715c7162ccfd7cd32da985d629bbd9c61.tar.gz gcc-e7a36e4715c7162ccfd7cd32da985d629bbd9c61.tar.bz2 | |
[PATCH] RISC-V: Support simplify (-1-x) for vector.
From: Yanzhang Wang <yanzhang.wang@intel.com>
The pattern is enabled for scalar but not for vector. The patch try to
make it consistent and will convert below code,
shortcut_for_riscv_vrsub_case_1_32:
vl1re32.v v1,0(a1)
vsetvli zero,a2,e32,m1,ta,ma
vrsub.vi v1,v1,-1
vs1r.v v1,0(a0)
ret
to,
shortcut_for_riscv_vrsub_case_1_32:
vl1re32.v v1,0(a1)
vsetvli zero,a2,e32,m1,ta,ma
vnot.v v1,v1
vs1r.v v1,0(a0)
ret
gcc/ChangeLog:
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1): Use
CONSTM1_RTX.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/simplify-vrsub.c: New test.
| -rw-r--r-- | gcc/simplify-rtx.cc | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c | 18 |
2 files changed, 19 insertions, 1 deletions
diff --git a/gcc/simplify-rtx.cc b/gcc/simplify-rtx.cc index d7315d8..eb1ac12 100644 --- a/gcc/simplify-rtx.cc +++ b/gcc/simplify-rtx.cc @@ -3071,7 +3071,7 @@ simplify_context::simplify_binary_operation_1 (rtx_code code, /* (-1 - a) is ~a, unless the expression contains symbolic constants, in which case not retaining additions and subtractions could cause invalid assembly to be produced. */ - if (trueop0 == constm1_rtx + if (trueop0 == CONSTM1_RTX (mode) && !contains_symbolic_reference_p (op1)) return simplify_gen_unary (NOT, mode, op1, mode); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c new file mode 100644 index 0000000..df87ed9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/simplify-vrsub.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +#define VRSUB_WITH_LMUL(LMUL, DTYPE) \ + vint##DTYPE##m##LMUL##_t \ + shortcut_for_riscv_vrsub_case_##LMUL##_##DTYPE \ + (vint##DTYPE##m##LMUL##_t v1, \ + size_t vl) \ + { \ + return __riscv_vrsub_vx_i##DTYPE##m##LMUL (v1, -1, vl); \ + } + +VRSUB_WITH_LMUL (1, 16) +VRSUB_WITH_LMUL (1, 32) + +/* { dg-final { scan-assembler-times {vnot\.v} 2 } } */ |