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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2024-09-04 21:34:31 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-09-04 21:34:31 -0600 |
| commit | de3ca363811a3974e4398ecdb1db2274efd61a1c (patch) | |
| tree | 00a02d65c7c4be38dada76e7857e9456eaf394ed | |
| parent | f9ca3fd1fe30f3ee6725bfe4a612e9a1234c11ac (diff) | |
| download | gcc-de3ca363811a3974e4398ecdb1db2274efd61a1c.zip gcc-de3ca363811a3974e4398ecdb1db2274efd61a1c.tar.gz gcc-de3ca363811a3974e4398ecdb1db2274efd61a1c.tar.bz2 | |
[PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection
These tests were checking that the output of the setCC instruction was bit
flipped, but it looks like they're really designed to test that
redundant sign extension elimination fires on conditionals from function
inputs. Jeff just posed a patch to clean this code up with trips up on
the arbitrary xori/snez instruction selection decision changing, so
let's just robustify the tests.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/sge.c: Adjust regex to match the input.
* gcc.target/riscv/sgeu.c: Likewise.
* gcc.target/riscv/sle.c: Likewise.
* gcc.target/riscv/sleu.c: Likewise.
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/sge.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/sgeu.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/sle.c | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/sleu.c | 2 |
4 files changed, 4 insertions, 4 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/sge.c b/gcc/testsuite/gcc.target/riscv/sge.c index 5f7e7ae..70f934c 100644 --- a/gcc/testsuite/gcc.target/riscv/sge.c +++ b/gcc/testsuite/gcc.target/riscv/sge.c @@ -8,5 +8,5 @@ sge (int x, int y) return x >= y; } -/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */ +/* { dg-final { scan-assembler "slt\\sa0,a0,a1" } } */ /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sgeu.c b/gcc/testsuite/gcc.target/riscv/sgeu.c index 234b9aa..0ff21cf 100644 --- a/gcc/testsuite/gcc.target/riscv/sgeu.c +++ b/gcc/testsuite/gcc.target/riscv/sgeu.c @@ -8,5 +8,5 @@ sgeu (unsigned int x, unsigned int y) return x >= y; } -/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */ +/* { dg-final { scan-assembler "sltu\\sa0,a0,a1" } } */ /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sle.c b/gcc/testsuite/gcc.target/riscv/sle.c index 3259c19..770840d 100644 --- a/gcc/testsuite/gcc.target/riscv/sle.c +++ b/gcc/testsuite/gcc.target/riscv/sle.c @@ -8,5 +8,5 @@ sle (int x, int y) return x <= y; } -/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */ +/* { dg-final { scan-assembler "sgt\\sa0,a0,a1" } } */ /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/sleu.c b/gcc/testsuite/gcc.target/riscv/sleu.c index 301b8c3..ae00ccc 100644 --- a/gcc/testsuite/gcc.target/riscv/sleu.c +++ b/gcc/testsuite/gcc.target/riscv/sleu.c @@ -8,5 +8,5 @@ sleu (unsigned int x, unsigned int y) return x <= y; } -/* { dg-final { scan-assembler "\\sxori\\sa0,a0,1\n\\sret\n" } } */ +/* { dg-final { scan-assembler "sgtu\\sa0,a0,a1"} } */ /* { dg-final { scan-assembler-not "andi|sext\\.w" } } */ |