diff options
| author | Toma Tabacu <toma.tabacu@imgtec.com> | 2017-01-18 10:57:17 +0000 |
|---|---|---|
| committer | Toma Tabacu <tomtab@gcc.gnu.org> | 2017-01-18 10:57:17 +0000 |
| commit | d5432112a747e8f885f216f6129c6f2e616a7bdd (patch) | |
| tree | d07625f70f9465ba9e7eb3d3459c2beefeb8e5bf | |
| parent | 01f9d481c5f6f37fcdab7212318f7a2e35591404 (diff) | |
| download | gcc-d5432112a747e8f885f216f6129c6f2e616a7bdd.zip gcc-d5432112a747e8f885f216f6129c6f2e616a7bdd.tar.gz gcc-d5432112a747e8f885f216f6129c6f2e616a7bdd.tar.bz2 | |
MIPS: Fix generation of Loongson-specific division and modulo instructions.
gcc
* config/mips/mips.h (ISA_HAS_DIV3): Remove unused macro.
(ISA_AVOID_DIV_HILO): New macro.
(ISA_HAS_DIV): Use new ISA_AVOID_DIV_HILO macro.
(ISA_HAS_DDIV): Likewise.
From-SVN: r244570
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 16 |
2 files changed, 18 insertions, 5 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3bd4acb..07f01a9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-01-18 Toma Tabacu <toma.tabacu@imgtec.com> + + * config/mips/mips.h (ISA_HAS_DIV3): Remove unused macro. + (ISA_AVOID_DIV_HILO): New macro. + (ISA_HAS_DIV): Use new ISA_AVOID_DIV_HILO macro. + (ISA_HAS_DDIV): Likewise. + 2017-01-18 Markus Trippelsdorf <markus@trippelsdorf.de> * doc/invoke.texi (fabi-version): Correct number of occurrences. diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index f91b43d..fbd7011 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -967,19 +967,25 @@ struct mips_cpu_info { /* ISA supports instructions DMUL, DMULU, DMUH, DMUHU. */ #define ISA_HAS_R6DMUL (TARGET_64BIT && mips_isa_rev >= 6) +/* For Loongson, it is preferable to use the Loongson-specific division and + modulo instructions instead of the regular (D)DIV(U) instruction, + because the former are faster and can also have the effect of reducing + code size. */ +#define ISA_AVOID_DIV_HILO ((TARGET_LOONGSON_2EF \ + || TARGET_LOONGSON_3A) \ + && !TARGET_MIPS16) + /* ISA supports instructions DDIV and DDIVU. */ #define ISA_HAS_DDIV (TARGET_64BIT \ && !TARGET_MIPS5900 \ + && !ISA_AVOID_DIV_HILO \ && mips_isa_rev <= 5) /* ISA supports instructions DIV and DIVU. This is always true, but the macro is needed for ISA_HAS_<D>DIV in mips.md. */ -#define ISA_HAS_DIV (mips_isa_rev <= 5) - -#define ISA_HAS_DIV3 ((TARGET_LOONGSON_2EF \ - || TARGET_LOONGSON_3A) \ - && !TARGET_MIPS16) +#define ISA_HAS_DIV (!ISA_AVOID_DIV_HILO \ + && mips_isa_rev <= 5) /* ISA supports instructions DIV, DIVU, MOD and MODU. */ #define ISA_HAS_R6DIV (mips_isa_rev >= 6) |