diff options
| author | Segher Boessenkool <segher@kernel.crashing.org> | 2019-06-05 01:32:21 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2019-06-05 01:32:21 +0200 |
| commit | cd9346a157c48d3fc5a059ca763ecb74178abeb8 (patch) | |
| tree | 01ce3b58ef955b7e9836b9a22e7b89f7b354f2a1 | |
| parent | 72e3386e136205dcc69e61e538b94643832cf22a (diff) | |
| download | gcc-cd9346a157c48d3fc5a059ca763ecb74178abeb8.zip gcc-cd9346a157c48d3fc5a059ca763ecb74178abeb8.tar.gz gcc-cd9346a157c48d3fc5a059ca763ecb74178abeb8.tar.bz2 | |
rs6000: Simplify <VSa> for VSX_TI
When used in VSX_TI, <VSa> is always just "wa".
* config/rs6000/vsx.md: Replace all <VSa> that are used with VSX_TI
with just "wa".
From-SVN: r271933
| -rw-r--r-- | gcc/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 8 |
2 files changed, 9 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f7eff36..213132f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,10 @@ 2019-06-04 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/vsx.md: Replace all <VSa> that are used with VSX_TI + with just "wa". + +2019-06-04 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/constraints.md (define_register_constraint "ww"): Delete. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index d082645..6255823 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -972,9 +972,9 @@ ;; special V1TI container class, which it is not appropriate to use vec_select ;; for the type. (define_insn "*vsx_le_permute_<mode>" - [(set (match_operand:VSX_TI 0 "nonimmediate_operand" "=<VSa>,<VSa>,Z,&r,&r,Q") + [(set (match_operand:VSX_TI 0 "nonimmediate_operand" "=wa,wa,Z,&r,&r,Q") (rotate:VSX_TI - (match_operand:VSX_TI 1 "input_operand" "<VSa>,Z,<VSa>,r,Q,r") + (match_operand:VSX_TI 1 "input_operand" "wa,Z,wa,r,Q,r") (const_int 64)))] "!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR" "@ @@ -988,10 +988,10 @@ (set_attr "type" "vecperm,vecload,vecstore,*,load,store")]) (define_insn_and_split "*vsx_le_undo_permute_<mode>" - [(set (match_operand:VSX_TI 0 "vsx_register_operand" "=<VSa>,<VSa>") + [(set (match_operand:VSX_TI 0 "vsx_register_operand" "=wa,wa") (rotate:VSX_TI (rotate:VSX_TI - (match_operand:VSX_TI 1 "vsx_register_operand" "0,<VSa>") + (match_operand:VSX_TI 1 "vsx_register_operand" "0,wa") (const_int 64)) (const_int 64)))] "!BYTES_BIG_ENDIAN && TARGET_VSX" |