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| author | Jakub Jelinek <jakub@redhat.com> | 2021-03-31 10:46:01 +0200 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2021-03-31 10:46:01 +0200 |
| commit | c001c194a2f73fb32461b597e91a35f9bbcf4414 (patch) | |
| tree | 32ccb59a39fc05d63562af45cac84bf6a888ba4e | |
| parent | a49a96f681bf13c6e77644d4507e867f00f93fe6 (diff) | |
| download | gcc-c001c194a2f73fb32461b597e91a35f9bbcf4414.zip gcc-c001c194a2f73fb32461b597e91a35f9bbcf4414.tar.gz gcc-c001c194a2f73fb32461b597e91a35f9bbcf4414.tar.bz2 | |
aarch64: Fix up *add<mode>3_poly_1 [PR99813]
As mentioned in the PR, Uai constraint stands for
aarch64_sve_scalar_inc_dec_immediate
while Uav for
aarch64_sve_addvl_addpl_immediate.
Both *add<mode>3_aarch64 and *add<mode>3_poly_1 patterns use
* return aarch64_output_sve_scalar_inc_dec (operands[2]);
* return aarch64_output_sve_addvl_addpl (operands[2]);
in that order, but the former with Uai,Uav order, while the
latter with Uav,Uai instead. This patch swaps the constraints
so that they match the output.
Co-authored-by: Richard Sandiford <richard.sandiford@arm.com>
2021-03-31 Jakub Jelinek <jakub@redhat.com>
Richard Sandiford <richard.sandiford@arm.com>
PR target/99813
* config/aarch64/aarch64.md (*add<mode>3_poly_1): Swap Uai and Uav
constraints on operands[2] and similarly 0 and rk constraints
on operands[1] corresponding to that.
* g++.target/aarch64/sve/pr99813.C: New test.
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/g++.target/aarch64/sve/pr99813.C | 27 |
2 files changed, 29 insertions, 2 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index b139c08..15bbc10 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2059,8 +2059,8 @@ [(set (match_operand:GPI 0 "register_operand" "=r,r,r,r,r,r,&r") (plus:GPI - (match_operand:GPI 1 "register_operand" "%rk,rk,rk,rk,rk,0,rk") - (match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "I,r,J,Uaa,Uav,Uai,Uat")))] + (match_operand:GPI 1 "register_operand" "%rk,rk,rk,rk,0,rk,rk") + (match_operand:GPI 2 "aarch64_pluslong_or_poly_operand" "I,r,J,Uaa,Uai,Uav,Uat")))] "TARGET_SVE && operands[0] != stack_pointer_rtx" "@ add\\t%<w>0, %<w>1, %2 diff --git a/gcc/testsuite/g++.target/aarch64/sve/pr99813.C b/gcc/testsuite/g++.target/aarch64/sve/pr99813.C new file mode 100644 index 0000000..f98b17c --- /dev/null +++ b/gcc/testsuite/g++.target/aarch64/sve/pr99813.C @@ -0,0 +1,27 @@ +// PR target/99813 +/* { dg-do assemble { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O3 -march=armv8.2-a+sve -fvect-cost-model=unlimited -fno-tree-dominator-opts -mtune=cortex-a72" } */ + +long a, b; +bool c[2][14][2][16], f[2][14][2][16]; +bool d; +char e[2][4][2][6]; +void g() { + a = 0; + for (int h = 0; h < 2; ++h) + for (int i = 0; i < 14; ++i) + for (int j = 0; j < 2; ++j) + for (int k = 0; k < 16; ++k) + c[h][i][j][k] = 0; + d = 0; + for (int h; h < 2; ++h) + for (int i = 0; i < 4; ++i) + for (int j = 0; j < 2; ++j) + for (int k = 0; k < 6; ++k) + e[h][i][j][k] = 6; + for (int h = 0; h < 2; ++h) + for (int i = 0; i < 14; ++i) + for (int j = 0; j < 2; ++j) + for (int k = 0; k < 16; ++k) + f[h][i][j][k] = b = 9; +} |