bpf: fix printing of memory operands in pseudoc asm dialect

The BPF backend was emitting memory operands in pseudo-C syntax
without surrounding parentheses.  These were being provided in the
corresponding instruction templates.

This was causing GCC emitting invalid instructions when finding inline
assembly with memory operands like:

	asm volatile (
	"r1 = *(u64 *)%[ctx_a];"
	"if r1 != 42 goto 1f;"
	"r1 = *(u64 *)%[ctx_b];"
	"if r1 != 42 goto 1f;"
	"r1 = *(u64 *)%[ctx_c];"
	"if r1 != 7 goto 1f;"
	"r1 /= 0;"
	"1:"
	:
	: [ctx_a]"m"(ctx.a),
	  [ctx_b]"m"(ctx.b),
	  [ctx_c]"m"(ctx.c)
	: "r1"
	);

This patch changes the backend to include the surrounding parentheses
in the printed representation of the memory operands (much like
surrounding brackets are included in normal asm syntax) and adapts the
impacted instruction templates accordingly.

Tested in target bpf-unknown-none, host x86_64-linux-gnu.

gcc/ChangeLog:

	* config/bpf/bpf.cc (bpf_print_operand_address): Include
	surrounding parenthesis around mem operands in pseudoc asm
	dialect.
	* config/bpf/bpf.md (*mov<MM:mode>): Adapt accordingly.
	(zero_extendhidi2): Likewise.
	(zero_extendqidi2): Likewise.
	(*extendsidi2): Likewise.
	(*extendsidi2): Likewise.
	(extendhidi2): Likewise.
	(extendqidi2): Likewise.
	(extendhisi2): Likewise.
	* config/bpf/atomic.md (atomic_add<AMO:mode>): Likewise.
	(atomic_and<AMO:mode>): Likewise.
	(atomic_or<AMO:mode>): Likewise.
	(atomic_xor<AMO:mode>): Likewise.
	(atomic_fetch_add<AMO:mode>): Likewise.
	(atomic_fetch_and<AMO:mode>): Likewise.
	(atomic_fetch_or<AMO:mode>): Likewise.
	(atomic_fetch_xor<AMO:mode>): Likewise.

3 files changed, 21 insertions, 24 deletions

diff --git a/gcc/config/bpf/atomic.md b/gcc/config/bpf/atomic.md
index 4c131ca..65bd5f2 100644
--- a/gcc/config/bpf/atomic.md
+++ b/gcc/config/bpf/atomic.md
@@ -34,7 +34,7 @@
           (match_operand:SI 2 "const_int_operand")] ;; Memory model.
          UNSPEC_AADD))]
   ""
-  "{xadd<mop>\t%0,%1|lock *(<smop> *)(%w0) += %w1}"
+  "{xadd<mop>\t%0,%1|lock *(<smop> *)%w0 += %w1}"
   [(set_attr "type" "atomic")])
 
 (define_insn "atomic_and<AMO:mode>"
@@ -45,7 +45,7 @@
           (match_operand:SI 2 "const_int_operand")] ;; Memory model.
          UNSPEC_AAND))]
   "bpf_has_v3_atomics"
-  "{aand<msuffix>\t%0,%1|lock *(<smop> *)(%w0) &= %w1}")
+  "{aand<msuffix>\t%0,%1|lock *(<smop> *)%w0 &= %w1}")
 
 (define_insn "atomic_or<AMO:mode>"
   [(set (match_operand:AMO 0 "memory_operand" "+m")
@@ -55,7 +55,7 @@
           (match_operand:SI 2 "const_int_operand")] ;; Memory model.
          UNSPEC_AOR))]
   "bpf_has_v3_atomics"
-  "{aor<msuffix>\t%0,%1|lock *(<smop> *)(%w0) %|= %w1}")
+  "{aor<msuffix>\t%0,%1|lock *(<smop> *)%w0 %|= %w1}")
 
 (define_insn "atomic_xor<AMO:mode>"
   [(set (match_operand:AMO 0 "memory_operand" "+m")
@@ -65,7 +65,7 @@
           (match_operand:SI 2 "const_int_operand")] ;; Memory model.
          UNSPEC_AXOR))]
   "bpf_has_v3_atomics"
-  "{axor<msuffix>\t%0,%1|lock *(<smop> *)(%w0) ^= %w1}")
+  "{axor<msuffix>\t%0,%1|lock *(<smop> *)%w0 ^= %w1}")
 
 ;;; Feching (read-modify-store) versions of atomic operations.
 
@@ -79,7 +79,7 @@
           (match_operand:AMO 3 "const_int_operand")] ;; Memory model
         UNSPEC_AFADD))]
   "bpf_has_v3_atomics"
-  "{afadd<msuffix>\t%1,%0|%w0 = atomic_fetch_add((<smop> *)(%1), %w0)}")
+  "{afadd<msuffix>\t%1,%0|%w0 = atomic_fetch_add((<smop> *)%1, %w0)}")
 
 (define_insn "atomic_fetch_and<AMO:mode>"
   [(set (match_operand:AMO 0 "register_operand" "=r")
@@ -91,7 +91,7 @@
           (match_operand:AMO 3 "const_int_operand")]
          UNSPEC_AFAND))]
   "bpf_has_v3_atomics"
-  "{afand<msuffix>\t%1,%0|%w0 = atomic_fetch_and((<smop> *)(%1), %w0)}")
+  "{afand<msuffix>\t%1,%0|%w0 = atomic_fetch_and((<smop> *)%1, %w0)}")
 
 (define_insn "atomic_fetch_or<AMO:mode>"
   [(set (match_operand:AMO 0 "register_operand" "=r")
@@ -103,7 +103,7 @@
           (match_operand:AMO 3 "const_int_operand")]
          UNSPEC_AFOR))]
   "bpf_has_v3_atomics"
-  "{afor<msuffix>\t%1,%0|%w0 = atomic_fetch_or((<smop> *)(%1), %w0)}")
+  "{afor<msuffix>\t%1,%0|%w0 = atomic_fetch_or((<smop> *)%1, %w0)}")
 
 (define_insn "atomic_fetch_xor<AMO:mode>"
   [(set (match_operand:AMO 0 "register_operand" "=r")
@@ -115,7 +115,7 @@
           (match_operand:AMO 3 "const_int_operand")]
          UNSPEC_AFXOR))]
   "bpf_has_v3_atomics"
-  "{afxor<msuffix>\t%1,%0|%w0 = atomic_fetch_xor((<smop> *)(%1), %w0)}")
+  "{afxor<msuffix>\t%1,%0|%w0 = atomic_fetch_xor((<smop> *)%1, %w0)}")
 
 ;; Weird suffixes used in pseudo-c atomic compare-exchange insns.
 (define_mode_attr pcaxsuffix [(SI "32_32") (DI "_64")])
diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc
index e6ea211..dd1bfe3 100644
--- a/gcc/config/bpf/bpf.cc
+++ b/gcc/config/bpf/bpf.cc
@@ -894,10 +894,9 @@ bpf_print_operand_address (FILE *file, rtx addr)
   switch (GET_CODE (addr))
     {
     case REG:
-      if (asm_dialect == ASM_NORMAL)
-	fprintf (file, "[");
+      fprintf (file, asm_dialect == ASM_NORMAL ? "[" : "(");
       bpf_print_register (file, addr, 0);
-      fprintf (file, asm_dialect == ASM_NORMAL ? "+0]" : "+0");
+      fprintf (file, asm_dialect == ASM_NORMAL ? "+0]" : "+0)");
       break;
     case PLUS:
       {
@@ -914,16 +913,14 @@ bpf_print_operand_address (FILE *file, rtx addr)
 		|| (GET_CODE (op1) == UNSPEC
 		    && XINT (op1, 1) == UNSPEC_CORE_RELOC)))
 	  {
-	    if (asm_dialect == ASM_NORMAL)
-	      fprintf (file, "[");
+            fprintf (file, asm_dialect == ASM_NORMAL ? "[" : "(");
 	    bpf_print_register (file, op0, 0);
 	    fprintf (file, "+");
 	    if (GET_CODE (op1) == UNSPEC)
 	      output_addr_const (file, XVECEXP (op1, 0, 0));
 	    else
 	      output_addr_const (file, op1);
-	    if (asm_dialect == ASM_NORMAL)
-	      fprintf (file, "]");
+            fprintf (file, asm_dialect == ASM_NORMAL ? "]" : ")");
 	  }
 	else
 	  fatal_insn ("invalid address in operand", addr);
diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md
index 9585932..a532e2a 100644
--- a/gcc/config/bpf/bpf.md
+++ b/gcc/config/bpf/bpf.md
@@ -282,7 +282,7 @@
   "@
    {and\t%0,0xffff|%0 &= 0xffff}
    *return bpf_output_move (operands, \"{mov\t%0,%1\;and\t%0,0xffff|%0 = %1;%0 &= 0xffff}\");
-   *return bpf_output_move (operands, \"{ldxh\t%0,%1|%0 = *(u16 *) (%1)}\");"
+   *return bpf_output_move (operands, \"{ldxh\t%0,%1|%0 = *(u16 *) %1}\");"
   [(set_attr "type" "alu,alu,ldx")])
 
 (define_insn "zero_extendqidi2"
@@ -292,7 +292,7 @@
   "@
    {and\t%0,0xff|%0 &= 0xff}
    *return bpf_output_move (operands, \"{mov\t%0,%1\;and\t%0,0xff|%0 = %1;%0 &= 0xff}\");
-   *return bpf_output_move (operands, \"{ldxb\t%0,%1|%0 = *(u8 *) (%1)}\");"
+   *return bpf_output_move (operands, \"{ldxb\t%0,%1|%0 = *(u8 *) %1}\");"
   [(set_attr "type" "alu,alu,ldx")])
 
 (define_insn "zero_extendsidi2"
@@ -302,7 +302,7 @@
   ""
   "@
    *return bpf_output_move (operands, bpf_has_alu32 ? \"{mov32\t%0,%1|%0 = %1}\" : \"{mov\t%0,%1\;and\t%0,0xffffffff|%0 = %1;%0 &= 0xffffffff}\");
-   *return bpf_output_move (operands, \"{ldxw\t%0,%1|%0 = *(u32 *) (%1)}\");"
+   *return bpf_output_move (operands, \"{ldxw\t%0,%1|%0 = *(u32 *) %1}\");"
   [(set_attr "type" "alu,ldx")])
 
 ;;; Sign-extension
@@ -329,7 +329,7 @@
   "bpf_has_smov"
   "@
    *return bpf_output_move (operands, \"{movs\t%0,%1,32|%0 = (s32) %1}\");
-   *return bpf_output_move (operands, \"{ldxsw\t%0,%1|%0 = *(s32 *) (%1)}\");"
+   *return bpf_output_move (operands, \"{ldxsw\t%0,%1|%0 = *(s32 *) %1}\");"
   [(set_attr "type" "alu,ldx")])
 
 (define_insn "extendhidi2"
@@ -338,7 +338,7 @@
   "bpf_has_smov"
   "@
    *return bpf_output_move (operands, \"{movs\t%0,%1,16|%0 = (s16) %1}\");
-   *return bpf_output_move (operands, \"{ldxsh\t%0,%1|%0 = *(s16 *) (%1)}\");"
+   *return bpf_output_move (operands, \"{ldxsh\t%0,%1|%0 = *(s16 *) %1}\");"
   [(set_attr "type" "alu,ldx")])
 
 (define_insn "extendqidi2"
@@ -347,7 +347,7 @@
   "bpf_has_smov"
   "@
    *return bpf_output_move (operands, \"{movs\t%0,%1,8|%0 = (s8) %1}\");
-   *return bpf_output_move (operands, \"{ldxsb\t%0,%1|%0 = *(s8 *) (%1)}\");"
+   *return bpf_output_move (operands, \"{ldxsb\t%0,%1|%0 = *(s8 *) %1}\");"
   [(set_attr "type" "alu,ldx")])
 
 (define_insn "extendhisi2"
@@ -384,11 +384,11 @@
         (match_operand:MM 1 "mov_src_operand"      " q,rIc,BC,r,I"))]
   ""
   "@
-   *return bpf_output_move (operands, \"{ldx<mop>\t%0,%1|%0 = *(<smop> *) (%1)}\");
+   *return bpf_output_move (operands, \"{ldx<mop>\t%0,%1|%0 = *(<smop> *) %1}\");
    *return bpf_output_move (operands, \"{mov\t%0,%1|%0 = %1}\");
    *return bpf_output_move (operands, \"{lddw\t%0,%1|%0 = %1 ll}\");
-   *return bpf_output_move (operands, \"{stx<mop>\t%0,%1|*(<smop> *) (%0) = %1}\");
-   *return bpf_output_move (operands, \"{st<mop>\t%0,%1|*(<smop> *) (%0) = %1}\");"
+   *return bpf_output_move (operands, \"{stx<mop>\t%0,%1|*(<smop> *) %0 = %1}\");
+   *return bpf_output_move (operands, \"{st<mop>\t%0,%1|*(<smop> *) %0 = %1}\");"
 [(set_attr "type" "ldx,alu,alu,stx,st")])
 
 ;;;; Shifts