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authorPan Li <pan2.li@intel.com>2024-03-30 20:03:18 +0800
committerPan Li <pan2.li@intel.com>2024-03-31 18:37:50 +0800
commitb313baba57f7e09f66b603e1e30dd4b48800693f (patch)
treeb9b9fa6512a73247e663c162d60fe59bc0f6ca38
parent46eb34a75a9d004ce776bba382fe8af0978cace7 (diff)
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RISC-V: Fix misspelled term builtin in error message
This patch would like to fix below misspelled term in error message. ../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error: misspelled term 'builtin function' in format; use 'built-in function' instead [-Werror=format-diag] 4592 | "builtin function %qE requires the V ISA extension", exp); The below tests are passed for this patch. * The riscv regression test on rvv.exp and riscv.exp. gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take the term built-in over builtin. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c: Adjust test dg-error. * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com>
-rw-r--r--gcc/config/riscv/riscv-vector-builtins.cc2
-rw-r--r--gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c2
-rw-r--r--gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index e07373d..db9246e 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -4589,7 +4589,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
if (!TARGET_VECTOR)
error_at (EXPR_LOCATION (exp),
- "builtin function %qE requires the V ISA extension", exp);
+ "built-in function %qE requires the V ISA extension", exp);
return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
index 520b2e5..a4cd67f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
@@ -5,5 +5,5 @@
size_t test_1 (size_t vl)
{
- return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
+ return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
index 9032d9d..06ed9a9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
@@ -19,5 +19,5 @@ test_2 ()
size_t
test_3 (size_t vl)
{
- return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
+ return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
}