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author | Craig Blackmore <craig.blackmore@embecosm.com> | 2024-06-22 22:07:06 -0600 |
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committer | Jeff Law <jlaw@ventanamicro.com> | 2024-06-22 22:07:06 -0600 |
commit | 77f3b3419d476e90a2b82dff2204466aba3b9c2c (patch) | |
tree | d1022f6cb60f8a54e780e0532c399aae974485a9 | |
parent | dba21b6a4085506fe730f2ff5d9b56f5944223bf (diff) | |
download | gcc-77f3b3419d476e90a2b82dff2204466aba3b9c2c.zip gcc-77f3b3419d476e90a2b82dff2204466aba3b9c2c.tar.gz gcc-77f3b3419d476e90a2b82dff2204466aba3b9c2c.tar.bz2 |
[PATCH] RISC-V: Fix unresolved mcpu-[67].c tests
These tests check the sched2 dump, so skip them for optimization levels
that do not enable sched2.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-6.c: Skip for -O0, -O1, -Og.
* gcc.target/riscv/mcpu-7.c: Likewise.
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/mcpu-6.c | 1 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/riscv/mcpu-7.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-6.c b/gcc/testsuite/gcc.target/riscv/mcpu-6.c index 96faa01..0126011 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-6.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-6.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ /* Verify -mtune has higher priority than -mcpu for pipeline model . */ /* { dg-options "-mcpu=sifive-u74 -mtune=rocket -fdump-rtl-sched2-details -march=rv32i -mabi=ilp32" } */ /* { dg-final { scan-rtl-dump "simple_return\[ \]+:alu" "sched2" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-7.c b/gcc/testsuite/gcc.target/riscv/mcpu-7.c index 6832323..6564363 100644 --- a/gcc/testsuite/gcc.target/riscv/mcpu-7.c +++ b/gcc/testsuite/gcc.target/riscv/mcpu-7.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ /* Verify -mtune has higher priority than -mcpu for pipeline model . */ /* { dg-options "-mcpu=sifive-s21 -mtune=sifive-u74 -fdump-rtl-sched2-details -march=rv32i -mabi=ilp32" } */ /* { dg-final { scan-rtl-dump "simple_return\[ \]+:sifive_7_B" "sched2" } } */ |