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| author | Andrew Stubbs <ams@baylibre.com> | 2024-08-07 15:35:18 +0000 |
|---|---|---|
| committer | Andrew Stubbs <ams@baylibre.com> | 2024-08-08 16:28:13 +0000 |
| commit | 715317331994d3d69395056f77bfe7ac613af009 (patch) | |
| tree | 04cfc15c7eebee138c7cbb4cf7e4601f075be693 | |
| parent | 89d2f3fefb0ae6dd4eb76f25009aa15735f09ed4 (diff) | |
| download | gcc-715317331994d3d69395056f77bfe7ac613af009.zip gcc-715317331994d3d69395056f77bfe7ac613af009.tar.gz gcc-715317331994d3d69395056f77bfe7ac613af009.tar.bz2 | |
amdgcn: Fix VGPR max count
The metadata for RDNA3 kernels allocates VGPRs in blocks of 12, which means the
maximum usable number of registers is 252. This patch prevents the compiler
from exceeding this artifical limit.
gcc/ChangeLog:
* config/gcn/gcn.cc (gcn_conditional_register_usage): Fix registers
remaining after maximum allocation using TARGET_VGPR_GRANULARITY.
| -rw-r--r-- | gcc/config/gcn/gcn.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/gcc/config/gcn/gcn.cc b/gcc/config/gcn/gcn.cc index b22132d..0725d15 100644 --- a/gcc/config/gcn/gcn.cc +++ b/gcc/config/gcn/gcn.cc @@ -2493,6 +2493,13 @@ gcn_secondary_reload (bool in_p, rtx x, reg_class_t rclass, static void gcn_conditional_register_usage (void) { + /* Some architectures have a register allocation granularity that does not + permit use of the full register count. */ + for (int i = 256 - (256 % TARGET_VGPR_GRANULARITY); + i < 256; + i++) + fixed_regs[VGPR_REGNO (i)] = call_used_regs[VGPR_REGNO (i)] = 1; + if (!cfun || !cfun->machine) return; |