rs6000,extend and document built-ins vec_test_lsbb_all_ones and vec_test_lsbb_all_zeros

The built-ins currently support vector unsigned char arguments.  Extend the
built-ins to also support vector signed char and vector bool char
arguments.

Add documentation for the Power 10 built-ins vec_test_lsbb_all_ones
and vec_test_lsbb_all_zeros.  The vec_test_lsbb_all_ones built-in
returns 1 if the least significant bit in each byte is a 1, returns
0 otherwise.  Similarly, vec_test_lsbb_all_zeros returns a 1 if
the least significant bit in each byte is a zero and 0 otherwise.

Add addtional test cases for the built-ins in files:
  gcc/testsuite/gcc.target/powerpc/lsbb.c
  gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c

gcc/ChangeLog:
	* config/rs6000/rs6000-overload.def (vec_test_lsbb_all_ones,
	vec_test_lsbb_all_zeros): Add built-in instances for vector signed
	char and vector bool char.
	* doc/extend.texi (vec_test_lsbb_all_ones,
	vec_test_lsbb_all_zeros): Add documentation for the
	existing built-ins.

gcc/testsuite/ChangeLog:gcc/testsuite/ChangeLog:
	* gcc.target/powerpc/lsbb-runnable.c: Add test cases for the vector
	signed char and vector bool char instances of
	vec_test_lsbb_all_zeros and vec_test_lsbb_all_ones built-ins.
	* gcc.target/powerpc/lsbb.c: Add compile test cases for the vector
	signed char and vector bool char instances of
	vec_test_lsbb_all_zeros and vec_test_lsbb_all_ones built-ins.

4 files changed, 158 insertions, 32 deletions

diff --git a/gcc/config/rs6000/rs6000-overload.def b/gcc/config/rs6000/rs6000-overload.def
index 87495ad..7d9e31c 100644
--- a/gcc/config/rs6000/rs6000-overload.def
+++ b/gcc/config/rs6000/rs6000-overload.def
@@ -4403,12 +4403,20 @@
     XXEVAL  XXEVAL_VUQ
 
 [VEC_TEST_LSBB_ALL_ONES, vec_test_lsbb_all_ones, __builtin_vec_xvtlsbb_all_ones]
+  signed int __builtin_vec_xvtlsbb_all_ones (vsc);
+    XVTLSBB_ONES LSBB_ALL_ONES_VSC
   signed int __builtin_vec_xvtlsbb_all_ones (vuc);
-    XVTLSBB_ONES
+    XVTLSBB_ONES LSBB_ALL_ONES_VUC
+  signed int __builtin_vec_xvtlsbb_all_ones (vbc);
+    XVTLSBB_ONES LSBB_ALL_ONES_VBC
 
 [VEC_TEST_LSBB_ALL_ZEROS, vec_test_lsbb_all_zeros, __builtin_vec_xvtlsbb_all_zeros]
+  signed int __builtin_vec_xvtlsbb_all_zeros (vsc);
+    XVTLSBB_ZEROS LSBB_ALL_ZEROS_VSC
   signed int __builtin_vec_xvtlsbb_all_zeros (vuc);
-    XVTLSBB_ZEROS
+    XVTLSBB_ZEROS LSBB_ALL_ZEROS_VUC
+  signed int __builtin_vec_xvtlsbb_all_zeros (vbc);
+    XVTLSBB_ZEROS LSBB_ALL_ZEROS_VBC
 
 [VEC_TRUNC, vec_trunc, __builtin_vec_trunc]
   vf __builtin_vec_trunc (vf);
diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
index af0c45b..2d795ba 100644
--- a/gcc/doc/extend.texi
+++ b/gcc/doc/extend.texi
@@ -23421,6 +23421,25 @@ signed long long will sign extend the rightmost byte of each doubleword.
 The following additional built-in functions are also available for the
 PowerPC family of processors, starting with ISA 3.1 (@option{-mcpu=power10}):
 
+@smallexample
+@exdent int vec_test_lsbb_all_ones (vector signed char);
+@exdent int vec_test_lsbb_all_ones (vector unsigned char);
+@exdent int vec_test_lsbb_all_ones (vector bool char);
+@end smallexample
+@findex vec_test_lsbb_all_ones
+
+The builtin @code{vec_test_lsbb_all_ones} returns 1 if the least significant
+bit in each byte is equal to 1.  It returns 0 otherwise.
+
+@smallexample
+@exdent int vec_test_lsbb_all_zeros (vector signed char);
+@exdent int vec_test_lsbb_all_zeros (vector unsigned char);
+@exdent int vec_test_lsbb_all_zeros (vector bool char);
+@end smallexample
+@findex vec_test_lsbb_all_zeros
+
+The builtin @code{vec_test_lsbb_all_zeros} returns 1 if the least significant
+bit in each byte is equal to zero.  It returns 0 otherwise.
 
 @smallexample
 @exdent vector unsigned long long int
diff --git a/gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c b/gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c
index 2e97cc1..3e4f71b 100644
--- a/gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c
+++ b/gcc/testsuite/gcc.target/powerpc/lsbb-runnable.c
@@ -17,7 +17,27 @@
 void abort (void);
 
 #define ITERS 7
-vector char input_vec[ITERS] = {
+vector signed char input_svec[ITERS] = {
+  {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+  {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
+  {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1},
+  {1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0},
+  {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+  {0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe},
+  {0xfe, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9}
+};
+
+vector unsigned char input_uvec[ITERS] = {
+  {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+  {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
+  {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1},
+  {1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0},
+  {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+  {0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe, 0xfe},
+  {0xfe, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9}
+};
+
+vector bool char input_bvec[ITERS] = {
   {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
   {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1},
   {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1},
@@ -30,37 +50,100 @@ vector char input_vec[ITERS] = {
 int expected_allzeros_results[ITERS] = {1, 0, 0, 0, 0, 1, 0};
 int expected_allones_results[ITERS] =  {0, 1, 0, 0, 1, 0, 0};
 
-int test_for_zeros(vector char vc) {
-  return vec_test_lsbb_all_zeros(vc);
+int test_for_zeros_uc(vector unsigned char vuc) {
+  return vec_test_lsbb_all_zeros(vuc);
+}
+
+int test_for_zeros_sc(vector signed char vsc) {
+  return vec_test_lsbb_all_zeros(vsc);
+}
+
+int test_for_zeros_bc(vector bool char vbc) {
+  return vec_test_lsbb_all_zeros(vbc);
+}
+
+int test_for_ones_sc(vector signed char vsc) {
+  return vec_test_lsbb_all_ones(vsc);
+}
+
+int test_for_ones_uc(vector unsigned char vuc) {
+  return vec_test_lsbb_all_ones(vuc);
 }
 
-int test_for_ones(vector char vc) {
-  return vec_test_lsbb_all_ones(vc);
+int test_for_ones_bc(vector bool char vbc) {
+  return vec_test_lsbb_all_ones(vbc);
 }
 
 int main ()
 {
-int allzeros,allones;
-int iter;
-int failcount=0;
-vector char srcvec;
-
-for (iter=0;iter<ITERS;iter++) {
-  srcvec = input_vec[iter];
-  allzeros = test_for_zeros(srcvec);
-  allones = test_for_ones(srcvec);
-  if (allzeros != expected_allzeros_results[iter]) {
-    printf("fail on allzero check. iter %d, result was %d \n", iter, allzeros);
-    failcount++;
+  int allzeros, allones;
+  int iter;
+  int failcount=0;
+  vector signed char srcvec_sc;
+  vector unsigned char srcvec_uc;
+  vector bool char srcvec_bc;
+
+  /* Signed type tests.  */
+  for (iter=0;iter<ITERS;iter++) {
+    srcvec_sc = input_svec[iter];
+    allzeros = test_for_zeros_sc(srcvec_sc);
+    allones = test_for_ones_sc(srcvec_sc);
+    if (allzeros != expected_allzeros_results[iter]) {
+      printf("fail on allzero signed char check. iter %d, result was %d \n",
+	     iter, allzeros);
+      failcount++;
+    }
+    if (allones != expected_allones_results[iter]) {
+      printf("fail on allones signed char check. iter %d, result was %d \n",
+	     iter, allones);
+      failcount++;
+    }
   }
-  if (allones != expected_allones_results[iter]) {
-    printf("fail on allones check. iter %d, result was %d \n", iter, allones);
-    failcount++;
+
+  if (failcount)
+    abort();
+
+  /* Unsigned type tests.  */
+  for (iter=0;iter<ITERS;iter++) {
+    srcvec_uc = input_uvec[iter];
+    allzeros = test_for_zeros_uc(srcvec_uc);
+    allones = test_for_ones_uc(srcvec_uc);
+    if (allzeros != expected_allzeros_results[iter]) {
+      printf("fail on allzero unsigned char check. iter %d, result was %d \n",
+	     iter, allzeros);
+      failcount++;
+    }
+    if (allones != expected_allones_results[iter]) {
+      printf("fail on allones unsigned char check. iter %d, result was %d \n",
+	     iter, allones);
+      failcount++;
+    }
   }
-}
 
-if (failcount)
-  abort();
-return 0;
+  if (failcount)
+    abort();
+
+  /* Bool char type tests.  */
+  for (iter=0;iter<ITERS;iter++) {
+    srcvec_bc = input_bvec[iter];
+    allzeros = test_for_zeros_bc(srcvec_bc);
+    allones = test_for_ones_bc(srcvec_bc);
+    if (allzeros != expected_allzeros_results[iter]) {
+      printf("fail on allzero bool char check. iter %d, result was %d \n",
+	     iter, allzeros);
+      failcount++;
+    }
+    if (allones != expected_allones_results[iter]) {
+      printf("fail on allones bool char check. iter %d, result was %d \n",
+	     iter, allones);
+      failcount++;
+    }
+  }
+
+  if (failcount)
+    abort();
+
+  
+  return 0;
 }
 
diff --git a/gcc/testsuite/gcc.target/powerpc/lsbb.c b/gcc/testsuite/gcc.target/powerpc/lsbb.c
index b5c0370..7f6e83d 100644
--- a/gcc/testsuite/gcc.target/powerpc/lsbb.c
+++ b/gcc/testsuite/gcc.target/powerpc/lsbb.c
@@ -6,19 +6,35 @@
     int vec_test_lsbb_all_ones (vector unsigned char);
  */
 
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-fno-inline -mdejagnu-cpu=power10 -O2" } */
+/* { dg-require-effective-target } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
 
-/* { dg-final { scan-assembler-times {\mxvtlsbb\M} 2 } } */
-/* { dg-final { scan-assembler-times {\msetbc\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mxvtlsbb\M} 6 } } */
+/* { dg-final { scan-assembler-times {\msetbc\M} 6 } } */
 
 #include <altivec.h>
 
-int test_for_zeros(vector char vc) {
+int test_for_zeros_signed(vector char vc) {
   return vec_test_lsbb_all_zeros(vc);
 }
 
-int test_for_ones(vector char vc) {
+int test_for_zeros_unsigned(vector unsigned char vuc) {
+  return vec_test_lsbb_all_zeros(vuc);
+}
+
+int test_for_zeros_bool(vector bool char vbc) {
+  return vec_test_lsbb_all_zeros(vbc);
+}
+
+int test_for_ones_signed(vector signed char vc) {
   return vec_test_lsbb_all_ones(vc);
 }
 
+int test_for_ones_unsigned(vector unsigned char vuc) {
+  return vec_test_lsbb_all_ones(vuc);
+}
+
+int test_for_ones_bool(vector bool char vbc) {
+  return vec_test_lsbb_all_ones(vbc);
+}
+