RISC-V: Fix asm check for Vector SAT_* due to middle-end change

The middle-end change makes the effect on the layout of the assembly
for vector SAT_*.  This patch would like to fix it and make it robust.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c: Adjust
	asm check and make it robust.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c: Ditto.
	* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c: Ditto.

Signed-off-by: Pan Li <pan2.li@intel.com>

99 files changed, 179 insertions, 294 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
index 348313b..d7d1dae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-1.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
index 425d4c7..4397c10 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-10.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
index 903ae36..b93b582 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-11.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
index b9db496..ec3c6af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-12.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
index 72d17c0..35f17c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
index 1aa4fbe..1169084 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-14.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
index 664fa61..9949047 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
index f752327..84c44f9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-16.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
index 352e22e..5f61acb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-17.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
index 7a1996d..eb4486c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-18.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
index c01c9f4..470eb6b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-19.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
index e4f7c64..b381c05 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-2.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
index 66ca4cd..6bd2c30 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-20.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
index 2e77b06..c525ba97 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-21.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
index 2e82404..41372d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
index 9283ce3..dddebb5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-23.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
index fcf7c92..ad5162d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-24.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
index a5ca922..39c20b3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-25.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
index 9d379ae..6eefaee 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-26.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
index 7b89fe1..78beb1b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-27.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
index f7c37df..369fa29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-28.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
index fbf57ff..e827cdd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
index a0847c9..97a9b1f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-3.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
index e8b6de3..af16f48 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-30.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
index 57f4bf2..0a8eabf 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-31.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
index 47a3bc1..38cbdfb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-32.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
index 3556761..8da2cb4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-4.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
index c89ecea..fe8a5a8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-5.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
index 0f0f454..1aeb24e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-6.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
index e0e311d..0d2b0e4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-7.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
index b76b231..168c269 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-8.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_add_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
index b13ff0a..d636302 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-9.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_add_uint8_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
index f0ce17d..5d214301 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-1.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
index fac9419..e50121b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-10.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
index 0c6afc3..de460c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-11.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
index 41fe3b8..96e06f0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-12.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
index a52e38a..dffe957 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-13.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
index 1ee8391..97b2e17e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-14.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
index d74a982..978c37c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-15.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
index 7028438..f43c571 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-16.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
index d44514c..f435b6e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-17.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
index 5dbbf20..74fe1e3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-18.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
index 4696753..b83b87b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-19.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
index c73413a..5499706 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-2.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
index b963ba1..0ae3c37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-20.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_5:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
index fc2682b..e16a0d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-21.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
index 4e51e4a..6b4bc69 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-22.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
index b16925e..6be7c76 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-23.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
index 9d99a4e..e9eb157 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-24.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_6:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
index 424551e..4980789 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-25.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
index 1103188..2a4d1cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-26.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
index 981c071..8c14d9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-27.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
index 1591537..32d3a62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-28.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_7:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
index 9c971f6..8c098ac 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-29.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
index 447b681..2af0485 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-3.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
index 09bcd0d..4a4fc74 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-30.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
index 704f560..5c912a3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-31.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
index 8011f6c..50aa0ae 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-32.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_8:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
index 2a57276..329dd23 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-33.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
index 4a7d7e5..a024ead 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-34.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
index cfad5d7..56216e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-35.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
index 721fd27..707bfd2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-36.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_9:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
index 1e3b5e7..e7dc212 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-37.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
index 4bc3205..b814830 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-38.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
index 3ec28cd..e6c6aaa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-39.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
index 5eca3de..21727fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-4.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
index 656c35c..716e58e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-40.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_10:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
index 942d2e9..e1d78af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-5.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
index c27fc4d..9911cbc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-6.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
index 8174359..8c83af1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-7.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
index 42cf16f..d76d754 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-8.c
@@ -8,10 +8,8 @@
 /*
 ** vec_sat_u_sub_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
index 9eb26d9..3b6b532 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub-9.c
@@ -8,9 +8,8 @@
 /*
 ** vec_sat_u_sub_uint8_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
-** vle8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma
+** ...
 ** vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
index ab22870..792d8a0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-1.c
@@ -8,11 +8,12 @@
 /*
 ** vec_sat_u_sub_trunc_uint8_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*ma
 ** ...
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
index 2c752e7..6778036 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-2.c
@@ -8,11 +8,12 @@
 /*
 ** vec_sat_u_sub_trunc_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma
 ** ...
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
index 7f89d70..04f2d0b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_sub_trunc-3.c
@@ -8,11 +8,12 @@
 /*
 ** vec_sat_u_sub_trunc_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e64,\s*m1,\s*ta,\s*ma
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*ma
 ** ...
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** vssubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[atx][0-9]+
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vncvt\.x\.x\.w\s+v[0-9]+,\s*v[0-9]+
 ** ...
 */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
index ae3e44c..60ab538 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-1.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
index f5084e5..2566450 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-10.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
index e2ab880..f90432b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
index e996c94..5330e19 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
index 49bdbdc..45d74ea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-13.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
index 3ff696e..c9ce878 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-14.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint32_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
index 7fca4a4..5529c71 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-15.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
index 201fcaa..6d773e9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-16.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint32_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
index 99a9600..808f62b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-17.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
index f1bd540..12a0e2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-18.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_3:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
index a80cefe..9c7979d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-19.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
index 2516468..cf6f404 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-2.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint32_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
index 9a4d261..2e497b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-20.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
index 5f0b71b..dd996d2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-21.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
index 059758b..a6c1254 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-22.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
index 6e094d0..2551b2f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-23.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
index 707b20b..bfcfa80 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-24.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_4:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
index 5df05f7..787c564 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-3.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
index 89dd653..b236c2a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-4.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint32_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint32_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
index 851a20e..1747585 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-5.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint16_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
index 8ae3bc2..fd30184b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-6.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint32_t_uint64_t_fmt_1:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
index a5b566b..dc9bbb5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-7.c
@@ -8,10 +8,9 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint16_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e8,\s*mf2,\s*ta,\s*ma
-** vle16\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint16_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
index a6df321..0525b8f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-8.c
@@ -8,12 +8,13 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint32_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e16,\s*mf2,\s*ta,\s*ma
-** vle32\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint32_t)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
index 7c68825..9662123 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-9.c
@@ -8,14 +8,17 @@
 /*
 ** vec_sat_u_trunc_uint8_t_uint64_t_fmt_2:
 ** ...
-** vsetvli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*e32,\s*mf2,\s*ta,\s*ma
-** vle64\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
+** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
+** ...
 ** vsetvli\s+zero,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma
+** ...
 ** vnclipu\.wi\s+v[0-9]+,\s*v[0-9]+,\s*0
-** vse8\.v\s+v[0-9]+,\s*0\([atx][0-9]+\)
 ** ...
 */
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint64_t)