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| author | Kito Cheng <kito.cheng@sifive.com> | 2024-08-27 21:27:02 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2024-08-28 09:13:18 +0800 |
| commit | 3cde331e9590944819621bcde41ddbffd9bbf0ba (patch) | |
| tree | 3b78a42dfd6d6c27e905c6bcaf9781d1c55c80f6 | |
| parent | fe5f652bab420eb372645281f7fe3e5aa1534d01 (diff) | |
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RISC-V: Add missing mode_idx for vrol and vror
We add pattern for vector rotate, but seems like we forgot adding
mode_idx which used in AVL propgation (riscv-avlprop.cc).
gcc/ChangeLog:
* config/riscv/vector.md (mode_idx): Add vrol and vror.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/rotr.c: New.
| -rw-r--r-- | gcc/config/riscv/vector.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c | 13 |
2 files changed, 14 insertions, 1 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 6667193..d067732 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -816,7 +816,7 @@ vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\ vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\ vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\ - vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz") + vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz,vrol,vror") (const_int 0) (eq_attr "type" "vimovvx,vfmovvf") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c new file mode 100644 index 0000000..055b28d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -fno-vect-cost-model -mrvv-vector-bits=zvl" } */ + +typedef int a; +void *b; +a c; +void d() { + a e = c, f =0; + short *g = b; + for (; f < e; f++) + *(g + f) = (255 & (*(g + f) >> 8)) | *(g + f) << 8; +} + |