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author | Pan Li <pan2.li@intel.com> | 2023-08-17 14:09:18 +0800 |
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committer | Pan Li <pan2.li@intel.com> | 2023-08-17 15:36:48 +0800 |
commit | 3a68ef2cccb8a7f15ca188dbffd754d112d75898 (patch) | |
tree | 5346fc92df65c2c6a966587e5fc1e0df6ce0a151 | |
parent | 3d903a26d7b6b4e32ad9f1f8c6fb5adf766c7cc7 (diff) | |
download | gcc-3a68ef2cccb8a7f15ca188dbffd754d112d75898.zip gcc-3a68ef2cccb8a7f15ca188dbffd754d112d75898.tar.gz gcc-3a68ef2cccb8a7f15ca188dbffd754d112d75898.tar.bz2 |
RISC-V: Support RVV VFREDOSUM.VS rounding mode intrinsic API
This patch would like to support the rounding mode API for the
VFREDOSUM.VS as the below samples.
* __riscv_vfredosum_vs_f32m1_f32m1_rm
* __riscv_vfredosum_vs_f32m1_f32m1_rm_m
Signed-off-by: Pan Li <pan2.li@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfredosum_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfredosum_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-redosum.c: New test.
4 files changed, 37 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 65f1d9c..ef29913 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -2539,6 +2539,7 @@ static CONSTEXPR const widen_reducop<UNSPEC_WREDUC_USUM> vwredsumu_obj; static CONSTEXPR const freducop<UNSPEC_UNORDERED> vfredusum_obj; static CONSTEXPR const freducop<UNSPEC_UNORDERED, HAS_FRM> vfredusum_frm_obj; static CONSTEXPR const freducop<UNSPEC_ORDERED> vfredosum_obj; +static CONSTEXPR const freducop<UNSPEC_ORDERED, HAS_FRM> vfredosum_frm_obj; static CONSTEXPR const reducop<SMAX> vfredmax_obj; static CONSTEXPR const reducop<SMIN> vfredmin_obj; static CONSTEXPR const widen_freducop<UNSPEC_UNORDERED> vfwredusum_obj; @@ -2797,6 +2798,7 @@ BASE (vwredsumu) BASE (vfredusum) BASE (vfredusum_frm) BASE (vfredosum) +BASE (vfredosum_frm) BASE (vfredmax) BASE (vfredmin) BASE (vfwredosum) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index fd1a84f..da8412b 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -241,6 +241,7 @@ extern const function_base *const vwredsumu; extern const function_base *const vfredusum; extern const function_base *const vfredusum_frm; extern const function_base *const vfredosum; +extern const function_base *const vfredosum_frm; extern const function_base *const vfredmax; extern const function_base *const vfredmin; extern const function_base *const vfwredosum; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 90a83c0..80e65bf 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -501,6 +501,7 @@ DEF_RVV_FUNCTION (vfredmax, reduc_alu, no_mu_preds, f_vs_ops) DEF_RVV_FUNCTION (vfredmin, reduc_alu, no_mu_preds, f_vs_ops) DEF_RVV_FUNCTION (vfredusum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops) +DEF_RVV_FUNCTION (vfredosum_frm, reduc_alu_frm, no_mu_preds, f_vs_ops) // 14.4. Vector Widening Floating-Point Reduction Instructions DEF_RVV_FUNCTION (vfwredosum, reduc_alu, no_mu_preds, wf_vs_ops) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c new file mode 100644 index 0000000..2e6a3c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-redosum.c @@ -0,0 +1,33 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +vfloat32m1_t +test_riscv_vfredosum_vs_f32m1_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfredosum_vs_f32m1_f32m1_rm (op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfredosum_vs_f32m1_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfredosum_vs_f32m1_f32m1_rm_m (mask, op1, op2, 1, vl); +} + +vfloat32m1_t +test_riscv_vfredosum_vs_f32m1_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfredosum_vs_f32m1_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfredosum_vs_f32m1_f32m1_m (vbool32_t mask, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfredosum_vs_f32m1_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ |