diff options
| author | Segher Boessenkool <segher@kernel.crashing.org> | 2019-06-04 18:30:47 +0200 |
|---|---|---|
| committer | Segher Boessenkool <segher@gcc.gnu.org> | 2019-06-04 18:30:47 +0200 |
| commit | 11d7bd360e26352aec26a12350b86bc9a3d5ec53 (patch) | |
| tree | ace6935b34a8b375912315c9bb9054341d0ab187 | |
| parent | cc998fd5f43a296e1a12bf4de63c4c9dd1d39cfa (diff) | |
| download | gcc-11d7bd360e26352aec26a12350b86bc9a3d5ec53.zip gcc-11d7bd360e26352aec26a12350b86bc9a3d5ec53.tar.gz gcc-11d7bd360e26352aec26a12350b86bc9a3d5ec53.tar.bz2 | |
rs6000: Delete VS_64reg
<VS_64reg> now always is "wa". Make that simplification.
* config/rs6000/vsx.md (define_mode_attr VS_64reg): Delete.
(*vsx_extract_<P:mode>_<VSX_D:mode>_load): Adjust.
(vsx_splat_<mode>_reg): Adjust.
From-SVN: r271917
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 9 |
2 files changed, 8 insertions, 7 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index aad3885..b9f1cb3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,11 @@ 2019-06-04 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/vsx.md (define_mode_attr VS_64reg): Delete. + (*vsx_extract_<P:mode>_<VSX_D:mode>_load): Adjust. + (vsx_splat_<mode>_reg): Adjust. + +2019-06-04 Segher Boessenkool <segher@kernel.crashing.org> + * config/rs6000/constraints.md (define_register_constraint "ws"): Delete. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Adjust. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 57f9963..60b3a8d 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -275,11 +275,6 @@ (V2DF "V4DF") (V1TI "V2TI")]) -;; Map register class for 64-bit element in 128-bit vector for normal register -;; to register moves -(define_mode_attr VS_64reg [(V2DF "wa") - (V2DI "wa")]) - ;; Iterators for loading constants with xxspltib (define_mode_iterator VSINT_84 [V4SI V2DI DI SI]) (define_mode_iterator VSINT_842 [V8HI V4SI V2DI]) @@ -3252,7 +3247,7 @@ ;; Optimize extracting a single scalar element from memory. (define_insn_and_split "*vsx_extract_<P:mode>_<VSX_D:mode>_load" - [(set (match_operand:<VS_scalar> 0 "register_operand" "=<VSX_D:VS_64reg>,wr") + [(set (match_operand:<VS_scalar> 0 "register_operand" "=wa,wr") (vec_select:<VSX_D:VS_scalar> (match_operand:VSX_D 1 "memory_operand" "m,m") (parallel [(match_operand:QI 2 "const_0_to_1_operand" "n,n")]))) @@ -4118,7 +4113,7 @@ (define_insn "vsx_splat_<mode>_reg" [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSX_D:VSa>,we") (vec_duplicate:VSX_D - (match_operand:<VS_scalar> 1 "gpc_reg_operand" "<VSX_D:VS_64reg>,b")))] + (match_operand:<VS_scalar> 1 "gpc_reg_operand" "wa,b")))] "VECTOR_MEM_VSX_P (<MODE>mode)" "@ xxpermdi %x0,%x1,%x1,0 |