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| author | Jakub Jelinek <jakub@redhat.com> | 2021-01-14 12:55:19 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2021-01-14 12:56:18 +0100 |
| commit | 0efdc7b31c2aeb3b0414a838e90014172b87302f (patch) | |
| tree | f293dad1cd762822a8d68ca81820fff61c1822de | |
| parent | 8f8762a2e8659c1db802ba001869085c1915498f (diff) | |
| download | gcc-0efdc7b31c2aeb3b0414a838e90014172b87302f.zip gcc-0efdc7b31c2aeb3b0414a838e90014172b87302f.tar.gz gcc-0efdc7b31c2aeb3b0414a838e90014172b87302f.tar.bz2 | |
i386: Fix the pmovzx SSE4.1 define_insn_and_split patterns [PR98670]
I've made two mistakes in the *sse4_1_zero_extend* define_insn_and_split
patterns. One is that when it uses vector_operand, it should use Bm rather
than m constraint, and the other one is that because it is a post-reload
splitter it needs isa attribute to select which alternatives are valid for
which ISAs. Sorry for messing this up.
2021-01-14 Jakub Jelinek <jakub@redhat.com>
PR target/98670
* config/i386/sse.md (*sse4_1_zero_extendv8qiv8hi2_3,
*sse4_1_zero_extendv4hiv4si2_3, *sse4_1_zero_extendv2siv2di2_3):
Use Bm instead of m for non-avx. Add isa attribute.
* gcc.target/i386/pr98670.c: New test.
| -rw-r--r-- | gcc/config/i386/sse.md | 15 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr98670.c | 16 |
2 files changed, 25 insertions, 6 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 7f03fc4..42d4c44 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -17721,7 +17721,7 @@ [(set (match_operand:V16QI 0 "register_operand" "=Yr,*x,v") (vec_select:V16QI (vec_concat:V32QI - (match_operand:V16QI 1 "vector_operand" "Yrm,*xm,vm") + (match_operand:V16QI 1 "vector_operand" "YrBm,*xBm,vm") (match_operand:V16QI 2 "const0_operand" "C,C,C")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand" "n,n,n")])))] @@ -17745,7 +17745,8 @@ emit_insn (gen_rtx_SET (operands[0], operands[1])); DONE; } -}) +} + [(set_attr "isa" "noavx,noavx,avx")]) (define_expand "<insn>v8qiv8hi2" [(set (match_operand:V8HI 0 "register_operand") @@ -18031,7 +18032,7 @@ [(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v") (vec_select:V8HI (vec_concat:V16HI - (match_operand:V8HI 1 "vector_operand" "Yrm,*xm,vm") + (match_operand:V8HI 1 "vector_operand" "YrBm,*xBm,vm") (match_operand:V8HI 2 "const0_operand" "C,C,C")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand" "n,n,n")])))] @@ -18053,7 +18054,8 @@ emit_insn (gen_rtx_SET (operands[0], operands[1])); DONE; } -}) +} + [(set_attr "isa" "noavx,noavx,avx")]) (define_insn "avx512f_<code>v8qiv8di2<mask_name>" [(set (match_operand:V8DI 0 "register_operand" "=v") @@ -18447,7 +18449,7 @@ [(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v") (vec_select:V4SI (vec_concat:V8SI - (match_operand:V4SI 1 "vector_operand" "Yrm,*xm,vm") + (match_operand:V4SI 1 "vector_operand" "YrBm,*xBm,vm") (match_operand:V4SI 2 "const0_operand" "C,C,C")) (match_parallel 3 "pmovzx_parallel" [(match_operand 4 "const_int_operand" "n,n,n")])))] @@ -18467,7 +18469,8 @@ emit_insn (gen_rtx_SET (operands[0], operands[1])); DONE; } -}) +} + [(set_attr "isa" "noavx,noavx,avx")]) (define_expand "<insn>v2siv2di2" [(set (match_operand:V2DI 0 "register_operand") diff --git a/gcc/testsuite/gcc.target/i386/pr98670.c b/gcc/testsuite/gcc.target/i386/pr98670.c new file mode 100644 index 0000000..34a0095 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr98670.c @@ -0,0 +1,16 @@ +/* PR target/98670 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include <x86intrin.h> + +void foo (__m128i); +int a[6]; + +void +bar (void) +{ + __m128i d = *(__m128i *) (a + 2); + __m128i e = _mm_unpacklo_epi16 (d, (__m128i) {}); + foo (e); +} |