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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-10-04 23:01:15 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-10-05 20:01:19 +0800 |
| commit | 0bda3f25147203d04724fa375daf3d1110da5c3f (patch) | |
| tree | 61a96c49fdf0c252724df24e5586d5e7315b43ff | |
| parent | 92cf0cf0856459bc980da96fd9c52b00857fa477 (diff) | |
| download | gcc-0bda3f25147203d04724fa375daf3d1110da5c3f.zip gcc-0bda3f25147203d04724fa375daf3d1110da5c3f.tar.gz gcc-0bda3f25147203d04724fa375daf3d1110da5c3f.tar.bz2 | |
RISC-V: Remove @ of vec_series
gcc/ChangeLog:
* config/riscv/autovec.md (@vec_series<mode>): Remove @.
(vec_series<mode>): Ditto.
* config/riscv/riscv-v.cc (expand_const_vector): Ditto.
(shuffle_decompress_patterns): Ditto.
| -rw-r--r-- | gcc/config/riscv/autovec.md | 2 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-v.cc | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index d6cf376..056f2c3 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -336,7 +336,7 @@ ;; - vadd.vx/vadd.vi ;; ------------------------------------------------------------------------- -(define_expand "@vec_series<mode>" +(define_expand "vec_series<mode>" [(match_operand:V_VLSI 0 "register_operand") (match_operand:<VEL> 1 "reg_or_int_operand") (match_operand:<VEL> 2 "reg_or_int_operand")] diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 29e138e..23633a2 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -1014,7 +1014,7 @@ expand_const_vector (rtx target, rtx src) rtx base, step; if (const_vec_series_p (src, &base, &step)) { - emit_insn (gen_vec_series (mode, target, base, step)); + expand_vec_series (target, base, step); return; } @@ -1171,7 +1171,7 @@ expand_const_vector (rtx target, rtx src) rtx step = CONST_VECTOR_ELT (src, 2); /* Step 1 - { base1, base1 + step, base1 + step * 2, ... } */ rtx tmp = gen_reg_rtx (mode); - emit_insn (gen_vec_series (mode, tmp, base1, step)); + expand_vec_series (tmp, base1, step); /* Step 2 - { base0, base1, base1 + step, base1 + step * 2, ... } */ scalar_mode elem_mode = GET_MODE_INNER (mode); if (!rtx_equal_p (base0, const0_rtx)) @@ -3020,7 +3020,7 @@ shuffle_decompress_patterns (struct expand_vec_perm_d *d) /* Generate { 0, 1, .... } mask. */ rtx vid = gen_reg_rtx (sel_mode); rtx vid_repeat = gen_reg_rtx (sel_mode); - emit_insn (gen_vec_series (sel_mode, vid, const0_rtx, const1_rtx)); + expand_vec_series (vid, const0_rtx, const1_rtx); rtx and_ops[] = {vid_repeat, vid, const1_rtx}; emit_vlmax_insn (code_for_pred_scalar (AND, sel_mode), BINARY_OP, and_ops); rtx const_vec = gen_const_vector_dup (sel_mode, 1); |